PrettyGoodRISCV/E-Series
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This commit is contained in:
John Terrell 2023-04-23 22:05:29 -07:00
parent 73ae766dc1
commit b82a6a9a79
Signed by untrusted user who does not match committer: johnt
GPG Key ID: 2E424258DD3731F4
9 changed files with 17 additions and 20 deletions
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2
src/Cpu/CSRs/MachineInformation.bsv
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@ -1,5 +1,3 @@
export MachineInformationCfg(..);
typedef struct { typedef struct {
Bit#(32) mvendorid; Bit#(32) mvendorid;
Bit#(xlen) marchid; Bit#(xlen) marchid;

1
src/Cpu/CSRs/MachineStatus.bsv
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@ -156,7 +156,6 @@ endinterface
module mkMachineStatus#(IsaCfg#(xlen) cfg)(MachineStatusIfc#(xlen)) module mkMachineStatus#(IsaCfg#(xlen) cfg)(MachineStatusIfc#(xlen))
provisos( provisos(
Add#(a__, 32, xlen),
MachineStatusBits#(xlen) MachineStatusBits#(xlen)
); );
Reg#(Bit#(xlen)) mstatus <- mkReg(defaultValue); Reg#(Bit#(xlen)) mstatus <- mkReg(defaultValue);

6
src/Cpu/Cpu.bsv
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@ -17,7 +17,7 @@ typedef struct {
} CpuCfg#(numeric type xlen, numeric type icacheFetchByteCount); } CpuCfg#(numeric type xlen, numeric type icacheFetchByteCount);
// //
// CpuIfc // Cpu
// //
interface CpuIfc#(numeric type xlen, numeric type icacheFetchByteCount); interface CpuIfc#(numeric type xlen, numeric type icacheFetchByteCount);
interface Get#(ICacheRequest#(xlen)) getCacheRequest; interface Get#(ICacheRequest#(xlen)) getCacheRequest;
@ -58,7 +58,7 @@ module mkCpu#(CpuCfg#(xlen, icacheFetchByteCount) cfg)(CpuIfc#(xlen, icacheFetch
// General purpose register (GPR) file // General purpose register (GPR) file
GprFileCfg#(xlen) gpr_cfg = GprFileCfg {}; GprFileCfg#(xlen) gpr_cfg = GprFileCfg {};
GprFile#(xlen) gpr <- mkGprFile(gpr_cfg); GprFileIfc#(xlen) gprfile <- mkGprFile(gpr_cfg);
// //
// INITIALIZATION // INITIALIZATION
@ -69,7 +69,7 @@ module mkCpu#(CpuCfg#(xlen, icacheFetchByteCount) cfg)(CpuIfc#(xlen, icacheFetch
// Zero the GPRs // Zero the GPRs
// //
for (gprInitIndex <= 0; gprInitIndex <= 32; gprInitIndex <= gprInitIndex + 1) for (gprInitIndex <= 0; gprInitIndex <= 32; gprInitIndex <= gprInitIndex + 1)
gpr.gprWritePort.write(truncate(gprInitIndex), 0); gprfile.gprWritePort.write(truncate(gprInitIndex), 0);
state <= FETCH; state <= FETCH;
endseq); endseq);

8
src/Cpu/CsrFile.bsv
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@ -38,7 +38,7 @@ interface CsrFileIfc#(numeric type xlen);
interface CsrWritePort#(xlen) csrWritePort; interface CsrWritePort#(xlen) csrWritePort;
interface CsrWritePermission csrWritePermission; interface CsrWritePermission csrWritePermission;
interface TrapController#(xlen) trapController; interface TrapControllerIfc#(xlen) trapController;
endinterface endinterface
module mkCsrFile#(IsaCfg#(xlen) cfg)(CsrFileIfc#(xlen)) module mkCsrFile#(IsaCfg#(xlen) cfg)(CsrFileIfc#(xlen))
@ -64,8 +64,8 @@ module mkCsrFile#(IsaCfg#(xlen) cfg)(CsrFileIfc#(xlen))
mconfigptr: 0 mconfigptr: 0
}; };
MachineStatusIfc#(xlen) mstatus <- mkMachineStatus(cfg); MachineStatusIfc#(xlen) mstatus <- mkMachineStatus(cfg);
MachineISAIfc#(xlen) misa <- mkMachineISA(cfg); MachineISAIfc#(xlen) misa <- mkMachineISA(cfg);
ReadOnly#(Bit#(xlen)) mcycle <- mkReadOnly(truncate(cycleCounter)); ReadOnly#(Bit#(xlen)) mcycle <- mkReadOnly(truncate(cycleCounter));
ReadOnly#(Bit#(xlen)) mtimer <- mkReadOnly(truncate(timeCounter)); ReadOnly#(Bit#(xlen)) mtimer <- mkReadOnly(truncate(timeCounter));
ReadOnly#(Bit#(xlen)) minstret <- mkReadOnly(truncate(retiredCounter)); ReadOnly#(Bit#(xlen)) minstret <- mkReadOnly(truncate(retiredCounter));
@ -316,7 +316,7 @@ module mkCsrFile#(IsaCfg#(xlen) cfg)(CsrFileIfc#(xlen))
// //
// trapController // trapController
// //
interface TrapController trapController; interface TrapControllerIfc trapController;
method ActionValue#(Bit#(xlen)) beginTrap(Bit#(xlen) trapProgramCounter, Trap#(xlen) trap); method ActionValue#(Bit#(xlen)) beginTrap(Bit#(xlen) trapProgramCounter, Trap#(xlen) trap);
Bit#(xlen) cause = 0; Bit#(xlen) cause = 0;

2
src/Cpu/DecodeStage_tb.bsv
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@ -23,7 +23,7 @@ module mkTopModule(Empty);
// //
GprFileCfg#(32) gprFileCfg32 = GprFileCfg { GprFileCfg#(32) gprFileCfg32 = GprFileCfg {
}; };
GprFile#(32) gprFile32 <- mkGprFile(gprFileCfg32); GprFileIfc#(32) gprFile32 <- mkGprFile(gprFileCfg32);
(* no_implicit_conditions *) (* no_implicit_conditions *)
rule test; rule test;

4
src/Cpu/GprFile.bsv
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@ -12,7 +12,7 @@ interface GprWritePort#(numeric type xlen);
method Action write(RVGPRIndex index, Bit#(xlen) value); method Action write(RVGPRIndex index, Bit#(xlen) value);
endinterface endinterface
interface GprFile#(numeric type xlen); interface GprFileIfc#(numeric type xlen);
interface GprReadPort#(xlen) gprReadPort1; interface GprReadPort#(xlen) gprReadPort1;
interface GprReadPort#(xlen) gprReadPort2; interface GprReadPort#(xlen) gprReadPort2;
@ -22,7 +22,7 @@ endinterface
typedef struct { typedef struct {
} GprFileCfg#(numeric type xlen); } GprFileCfg#(numeric type xlen);
module mkGprFile#(GprFileCfg#(xlen) cfg)(GprFile#(xlen)); module mkGprFile#(GprFileCfg#(xlen) cfg)(GprFileIfc#(xlen));
Vector#(32, Reg#(Bit#(xlen))) reg_file <- replicateM(mkReg(0)); Vector#(32, Reg#(Bit#(xlen))) reg_file <- replicateM(mkReg(0));
interface GprReadPort gprReadPort1; interface GprReadPort gprReadPort1;

2
src/Cpu/Trap.bsv
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@ -4,7 +4,7 @@ typedef struct {
Bit#(xlen) tval; Bit#(xlen) tval;
} Trap#(numeric type xlen) deriving(Bits, Eq, FShow); } Trap#(numeric type xlen) deriving(Bits, Eq, FShow);
interface TrapController#(numeric type xlen); interface TrapControllerIfc#(numeric type xlen);
method ActionValue#(Bit#(xlen)) beginTrap(Bit#(xlen) trap_program_counter, Trap#(xlen) trap); method ActionValue#(Bit#(xlen)) beginTrap(Bit#(xlen) trap_program_counter, Trap#(xlen) trap);
method ActionValue#(Bit#(xlen)) endTrap; method ActionValue#(Bit#(xlen)) endTrap;
endinterface endinterface

4
src/ESeries.bsv
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@ -4,7 +4,7 @@
import Soc::*; import Soc::*;
//!topmodule mkE001 //!topmodule mkE001
module mkE001(SocIfc#(32, 32)); module mkE001(Soc#(32, 32));
SocCfg#(32, 32) cfg = SocCfg { SocCfg#(32, 32) cfg = SocCfg {
cpu_cfg: CpuCfg { cpu_cfg: CpuCfg {
initial_program_counter: 'h8000_0000 initial_program_counter: 'h8000_0000
@ -14,7 +14,7 @@ module mkE001(SocIfc#(32, 32));
endmodule endmodule
//!topmodule mkE003 //!topmodule mkE003
module mkE003(SocIfc#(64, 32)); module mkE003(Soc#(64, 32));
SocCfg#(64, 32) cfg = SocCfg{ SocCfg#(64, 32) cfg = SocCfg{
cpu_cfg: CpuCfg { cpu_cfg: CpuCfg {
initial_program_counter: 'h8000_0000 initial_program_counter: 'h8000_0000

8
src/Soc.bsv
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@ -1,5 +1,5 @@
import Cpu::*; import Cpu::*;
export CpuCfg(..), mkSoc, SocCfg(..), SocIfc(..); export CpuCfg(..), mkSoc, SocCfg(..), Soc(..);
// //
// SocConfig // SocConfig
@ -9,14 +9,14 @@ typedef struct {
} SocCfg#(numeric type xlen, numeric type ifetchByteCount); } SocCfg#(numeric type xlen, numeric type ifetchByteCount);
// //
// SocIfc // Soc
// //
interface SocIfc#(numeric type xlen, numeric type ifetchByteCount); interface Soc#(numeric type xlen, numeric type ifetchByteCount);
endinterface endinterface
// //
// mkSoc() // mkSoc()
// //
module mkSoc#(SocCfg#(xlen, ifetchByteCount) cfg)(SocIfc#(xlen, ifetchByteCount)); module mkSoc#(SocCfg#(xlen, ifetchByteCount) cfg)(Soc#(xlen, ifetchByteCount));
let cpu <- mkCpu(cfg.cpu_cfg); let cpu <- mkCpu(cfg.cpu_cfg);
endmodule endmodule