diff --git a/src/Cpu/CSRs/MachineInformation.bsv b/src/Cpu/CSRs/MachineInformation.bsv index fe2ccde..2b7f84b 100644 --- a/src/Cpu/CSRs/MachineInformation.bsv +++ b/src/Cpu/CSRs/MachineInformation.bsv @@ -1,5 +1,3 @@ -export MachineInformationCfg(..); - typedef struct { Bit#(32) mvendorid; Bit#(xlen) marchid; diff --git a/src/Cpu/CSRs/MachineStatus.bsv b/src/Cpu/CSRs/MachineStatus.bsv index 7f99aec..d74cbca 100644 --- a/src/Cpu/CSRs/MachineStatus.bsv +++ b/src/Cpu/CSRs/MachineStatus.bsv @@ -156,7 +156,6 @@ endinterface module mkMachineStatus#(IsaCfg#(xlen) cfg)(MachineStatusIfc#(xlen)) provisos( - Add#(a__, 32, xlen), MachineStatusBits#(xlen) ); Reg#(Bit#(xlen)) mstatus <- mkReg(defaultValue); diff --git a/src/Cpu/Cpu.bsv b/src/Cpu/Cpu.bsv index d8f0c50..2ccc876 100644 --- a/src/Cpu/Cpu.bsv +++ b/src/Cpu/Cpu.bsv @@ -17,7 +17,7 @@ typedef struct { } CpuCfg#(numeric type xlen, numeric type icacheFetchByteCount); // -// CpuIfc +// Cpu // interface CpuIfc#(numeric type xlen, numeric type icacheFetchByteCount); interface Get#(ICacheRequest#(xlen)) getCacheRequest; @@ -58,7 +58,7 @@ module mkCpu#(CpuCfg#(xlen, icacheFetchByteCount) cfg)(CpuIfc#(xlen, icacheFetch // General purpose register (GPR) file GprFileCfg#(xlen) gpr_cfg = GprFileCfg {}; - GprFile#(xlen) gpr <- mkGprFile(gpr_cfg); + GprFileIfc#(xlen) gprfile <- mkGprFile(gpr_cfg); // // INITIALIZATION @@ -69,7 +69,7 @@ module mkCpu#(CpuCfg#(xlen, icacheFetchByteCount) cfg)(CpuIfc#(xlen, icacheFetch // Zero the GPRs // for (gprInitIndex <= 0; gprInitIndex <= 32; gprInitIndex <= gprInitIndex + 1) - gpr.gprWritePort.write(truncate(gprInitIndex), 0); + gprfile.gprWritePort.write(truncate(gprInitIndex), 0); state <= FETCH; endseq); diff --git a/src/Cpu/CsrFile.bsv b/src/Cpu/CsrFile.bsv index eb17ad1..a3c4a9a 100644 --- a/src/Cpu/CsrFile.bsv +++ b/src/Cpu/CsrFile.bsv @@ -38,7 +38,7 @@ interface CsrFileIfc#(numeric type xlen); interface CsrWritePort#(xlen) csrWritePort; interface CsrWritePermission csrWritePermission; - interface TrapController#(xlen) trapController; + interface TrapControllerIfc#(xlen) trapController; endinterface module mkCsrFile#(IsaCfg#(xlen) cfg)(CsrFileIfc#(xlen)) @@ -64,8 +64,8 @@ module mkCsrFile#(IsaCfg#(xlen) cfg)(CsrFileIfc#(xlen)) mconfigptr: 0 }; - MachineStatusIfc#(xlen) mstatus <- mkMachineStatus(cfg); - MachineISAIfc#(xlen) misa <- mkMachineISA(cfg); + MachineStatusIfc#(xlen) mstatus <- mkMachineStatus(cfg); + MachineISAIfc#(xlen) misa <- mkMachineISA(cfg); ReadOnly#(Bit#(xlen)) mcycle <- mkReadOnly(truncate(cycleCounter)); ReadOnly#(Bit#(xlen)) mtimer <- mkReadOnly(truncate(timeCounter)); ReadOnly#(Bit#(xlen)) minstret <- mkReadOnly(truncate(retiredCounter)); @@ -316,7 +316,7 @@ module mkCsrFile#(IsaCfg#(xlen) cfg)(CsrFileIfc#(xlen)) // // trapController // - interface TrapController trapController; + interface TrapControllerIfc trapController; method ActionValue#(Bit#(xlen)) beginTrap(Bit#(xlen) trapProgramCounter, Trap#(xlen) trap); Bit#(xlen) cause = 0; diff --git a/src/Cpu/DecodeStage_tb.bsv b/src/Cpu/DecodeStage_tb.bsv index 3e914fd..8fadafd 100644 --- a/src/Cpu/DecodeStage_tb.bsv +++ b/src/Cpu/DecodeStage_tb.bsv @@ -23,7 +23,7 @@ module mkTopModule(Empty); // GprFileCfg#(32) gprFileCfg32 = GprFileCfg { }; - GprFile#(32) gprFile32 <- mkGprFile(gprFileCfg32); + GprFileIfc#(32) gprFile32 <- mkGprFile(gprFileCfg32); (* no_implicit_conditions *) rule test; diff --git a/src/Cpu/GprFile.bsv b/src/Cpu/GprFile.bsv index 3cd2d8d..60e96ba 100644 --- a/src/Cpu/GprFile.bsv +++ b/src/Cpu/GprFile.bsv @@ -12,7 +12,7 @@ interface GprWritePort#(numeric type xlen); method Action write(RVGPRIndex index, Bit#(xlen) value); endinterface -interface GprFile#(numeric type xlen); +interface GprFileIfc#(numeric type xlen); interface GprReadPort#(xlen) gprReadPort1; interface GprReadPort#(xlen) gprReadPort2; @@ -22,7 +22,7 @@ endinterface typedef struct { } GprFileCfg#(numeric type xlen); -module mkGprFile#(GprFileCfg#(xlen) cfg)(GprFile#(xlen)); +module mkGprFile#(GprFileCfg#(xlen) cfg)(GprFileIfc#(xlen)); Vector#(32, Reg#(Bit#(xlen))) reg_file <- replicateM(mkReg(0)); interface GprReadPort gprReadPort1; diff --git a/src/Cpu/Trap.bsv b/src/Cpu/Trap.bsv index f1e4179..7854c75 100644 --- a/src/Cpu/Trap.bsv +++ b/src/Cpu/Trap.bsv @@ -4,7 +4,7 @@ typedef struct { Bit#(xlen) tval; } Trap#(numeric type xlen) deriving(Bits, Eq, FShow); -interface TrapController#(numeric type xlen); +interface TrapControllerIfc#(numeric type xlen); method ActionValue#(Bit#(xlen)) beginTrap(Bit#(xlen) trap_program_counter, Trap#(xlen) trap); method ActionValue#(Bit#(xlen)) endTrap; endinterface diff --git a/src/ESeries.bsv b/src/ESeries.bsv index 4281553..3944d5d 100644 --- a/src/ESeries.bsv +++ b/src/ESeries.bsv @@ -4,7 +4,7 @@ import Soc::*; //!topmodule mkE001 -module mkE001(SocIfc#(32, 32)); +module mkE001(Soc#(32, 32)); SocCfg#(32, 32) cfg = SocCfg { cpu_cfg: CpuCfg { initial_program_counter: 'h8000_0000 @@ -14,7 +14,7 @@ module mkE001(SocIfc#(32, 32)); endmodule //!topmodule mkE003 -module mkE003(SocIfc#(64, 32)); +module mkE003(Soc#(64, 32)); SocCfg#(64, 32) cfg = SocCfg{ cpu_cfg: CpuCfg { initial_program_counter: 'h8000_0000 diff --git a/src/Soc.bsv b/src/Soc.bsv index f03790f..4f2f843 100644 --- a/src/Soc.bsv +++ b/src/Soc.bsv @@ -1,5 +1,5 @@ import Cpu::*; -export CpuCfg(..), mkSoc, SocCfg(..), SocIfc(..); +export CpuCfg(..), mkSoc, SocCfg(..), Soc(..); // // SocConfig @@ -9,14 +9,14 @@ typedef struct { } SocCfg#(numeric type xlen, numeric type ifetchByteCount); // -// SocIfc +// Soc // -interface SocIfc#(numeric type xlen, numeric type ifetchByteCount); +interface Soc#(numeric type xlen, numeric type ifetchByteCount); endinterface // // mkSoc() // -module mkSoc#(SocCfg#(xlen, ifetchByteCount) cfg)(SocIfc#(xlen, ifetchByteCount)); +module mkSoc#(SocCfg#(xlen, ifetchByteCount) cfg)(Soc#(xlen, ifetchByteCount)); let cpu <- mkCpu(cfg.cpu_cfg); endmodule