397 lines
14 KiB
Plaintext
397 lines
14 KiB
Plaintext
import Cntrs::*;
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import GetPut::*;
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import ReadOnly::*;
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import Trap::*;
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import IsaCfg::*;
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import MachineInformation::*;
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import MachineStatus::*;
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import RV_ISA::*;
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typedef struct {
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Bit#(xlen) value;
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Bool denied;
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} CsrReadResult#(numeric type xlen) deriving(Bits, Eq, FShow);
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typedef struct {
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Bool denied;
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} CsrWriteResult deriving(Bits, Eq, FShow);
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interface CsrReadPort#(numeric type xlen);
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method ActionValue#(CsrReadResult#(xlen)) read(RVCsrIndex index);
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endinterface
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interface CsrWritePort#(numeric type xlen);
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method ActionValue#(CsrWriteResult) write(RVCsrIndex index, Bit#(xlen) value);
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endinterface
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interface CsrWritePermission;
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method Bool isWriteable(RVCsrIndex index);
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endinterface
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interface CsrFile#(numeric type xlen);
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method Action incrementCycleCounters;
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method Action incrementInstructionsRetiredCounter;
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interface CsrReadPort#(xlen) csrReadPort;
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interface CsrWritePort#(xlen) csrWritePort;
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interface CsrWritePermission csrWritePermission;
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interface TrapController#(xlen) trapController;
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endinterface
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typedef struct {
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IsaCfg#(xlen) isa_cfg;
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} CsrFileCfg#(numeric type xlen);
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module mkCsrFile#(CsrFileCfg#(xlen) cfg)(CsrFile#(xlen));
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Reg#(RVPrivilegeLevel) currentPriv <- mkReg(priv_MACHINE);
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// Counters
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Count#(Bit#(64)) cycleCounter <- mkCount(0);
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Count#(Bit#(64)) timeCounter <- mkCount(0);
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Count#(Bit#(64)) retiredCounter <- mkCount(0);
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// Csrs
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// MINFO (mvendorid, marchid, mpimpid, mhardit, mconfigptr)
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MachineInformationCfg#(xlen) machineInfoCfg = MachineInformationCfg {
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mvendorid: 0,
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marchid: 0,
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mimpid: 0,
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mhartid: 0,
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mconfigptr: 0
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};
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MachineStatusIfc#(xlen) mstatus <- mkMachineStatus(cfg);
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/*
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ReadOnly#(Bit#(xlen)) mcycle <- mkReadOnly(truncate(cycleCounter));
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ReadOnly#(Bit#(xlen)) mtimer <- mkReadOnly(truncate(timeCounter));
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ReadOnly#(Bit#(xlen)) minstret <- mkReadOnly(truncate(retiredCounter));
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*/
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/*
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if (valueof(xlen) == 32) begin
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ReadOnly#(Bit#(xlen)) mcycleh <- mkReadOnly(truncateLSB(cycleCounter));
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ReadOnly#(Bit#(xlen)) mtimeh <- mkReadOnly(truncateLSB(timeCounter));
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ReadOnly#(Bit#(xlen)) minstreth <- mkReadOnly(truncateLSB(retiredCounter));
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end
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*/
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Reg#(Bit#(xlen)) mcause <- mkReg(0);
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Reg#(Bit#(xlen)) mtvec <- mkReg('hC0DEC0DE);
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Reg#(Bit#(xlen)) mepc <- mkReg(0);
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Reg#(Bit#(xlen)) mscratch <- mkReg(0);
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Reg#(Bit#(xlen)) mip <- mkReg(0);
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Reg#(Bit#(xlen)) mie <- mkReg(0);
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Reg#(Bit#(xlen)) mtval <- mkReg(0);
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Reg#(Bit#(xlen)) mideleg <- mkReg(0);
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Reg#(Bit#(xlen)) medeleg <- mkReg(0);
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Reg#(Bit#(xlen)) sideleg <- mkReg(0);
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Reg#(Bit#(xlen)) sedeleg <- mkReg(0);
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function Bool isWARLIgnore(RVCsrIndex index);
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Bool result = False;
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if ((index >= csr_PMPADDR0 && index <= csr_PMPADDR63) ||
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(index >= csr_PMPCFG0 && index <= csr_PMPCFG15) ||
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index == csr_SATP ||
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index == csr_MIDELEG ||
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index == csr_MEDELEG) begin
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result = True;
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end
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return result;
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endfunction
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function RVCsrIndex getIndex(RVPrivilegeLevel privilege_level, RVCsrIndexOffset offset);
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RVCsrIndex index = 0;
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index[9:8] = privilege_level[1:0];
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index[7:0] = offset;
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return index;
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endfunction
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// Based on fv_new_priv_on_exception from Flute processor.
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function RVPrivilegeLevel getTrapPrivilegeLevel(Trap#(xlen) trap);
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let trap_privilege_level = priv_MACHINE;
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if (currentPriv < priv_MACHINE) begin
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if (cfg.s_mode_supported) begin // S mode supported?
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// See if this trap should be delegated to SUPERVISOR mode
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let delegated = (trap.isInterrupt ?
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(mideleg[trap.cause] == 0 ? False : True) :
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(medeleg[trap.cause] == 0 ? False : True));
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if (delegated) begin
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trap_privilege_level = priv_SUPERVISOR;
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// If the current priv mode is U, and user mode traps are supported,
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// then consult sedeleg/sideleg to determine if delegated to USER mode.
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if (currentPriv == priv_USER && cfg.u_level_interrupts_supported) begin
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delegated = (trap.isInterrupt ?
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(sideleg[trap.cause] == 0 ? False : True) :
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(sedeleg[trap.cause] == 0 ? False : True));
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if (delegated) begin
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trap_privilege_level = priv_USER;
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end
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end
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end
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end else begin // S mode *NOT* supported
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// If user mode traps are supported, then consult sedeleg/sideleg to determine
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// if delegated to USER mode.
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if (cfg.u_level_interrupts_supported) begin
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let delegated = (trap.isInterrupt ?
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(mideleg[trap.cause] == 0 ? False : True) :
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(medeleg[trap.cause] == 0 ? False : True));
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if (delegated) begin
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trap_privilege_level = priv_USER;
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end
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end
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end
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end
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return trap_privilege_level;
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endfunction
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//
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// readInternal
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//
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function ActionValue#(CsrReadResult#(xlen)) readInternal(RVCsrIndex index);
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actionvalue
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let result = CsrReadResult {
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value: 0,
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denied: False
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};
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if (!isWARLIgnore(index)) begin
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case(index)
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// Machine Information Registers (MRO)
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/*
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csr_MVENDORID: result.value = extend(machineInfoCfg.mvendorid);
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*/
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csr_MARCHID: result.value = machineInfoCfg.marchid;
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csr_MIMPID: result.value = machineInfoCfg.mimpid;
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csr_MHARTID: result.value = machineInfoCfg.mhartid;
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csr_MISA: result.value = pack(cfg);
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csr_MCAUSE: result.value = mcause;
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csr_MTVEC: result.value = mtvec;
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csr_MEPC: result.value = mepc;
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csr_MTVAL: result.value = mtval;
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csr_MIDELEG: result.value = mideleg;
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csr_MEDELEG: result.value = medeleg;
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csr_MSTATUS: begin
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let mstatus_ <- mstatus.getMachineStatus.get;
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result.value = pack(mstatus_);
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end
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/*
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csr_MCYCLE, csr_CYCLE: begin
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result.value = mcycle;
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end
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*/
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csr_MSCRATCH: result.value = mscratch;
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csr_MIP: result.value = mip;
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csr_MIE: result.value = mie;
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// !bugbug - TSELECT is hardcoded to all 1s. This is to keep
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// the ISA debug test happy. It *should* report a
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// pass if reading TSELECT failed with a trap (to reflect what's in the spec)
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// This is a bug in the debug test.
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csr_TSELECT: result.value = 'hFFFF_FFFF;
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default: begin
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result.denied = True;
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end
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endcase
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end
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$display("---- Csr Read Index : ", fshow(index));
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$display("---- Csr Read Result: ", fshow(result));
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return result;
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endactionvalue
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endfunction
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//
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// writeInternal
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//
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function ActionValue#(CsrWriteResult) writeInternal(RVCsrIndex index, Bit#(xlen) value);
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actionvalue
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let result = CsrWriteResult {
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denied: False
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};
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// Access and write to read-only Csr check.
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if (!isWARLIgnore(index)) begin
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case(index)
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csr_MCAUSE: mcause <= value;
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csr_MCYCLE: cycleCounter <= zeroExtend(value);
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csr_MEPC: mepc <= value;
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csr_MISA: begin
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// No-Op
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end
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csr_MSCRATCH: mscratch <= value;
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csr_MSTATUS: mstatus.unpack(value);
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csr_MTVAL: mtval <= value;
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csr_MTVEC: mtvec <= value;
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csr_MIE: mie <= value;
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csr_MIP: mip <= value;
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csr_TSELECT: begin
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// No-Op
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end
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default: result.denied = True;
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endcase
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end
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$display("---- Csr Write Index : ", fshow(index));
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$display("---- Csr Write Value : ", value);
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$display("---- Csr Write Result: ", fshow(result));
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return result;
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endactionvalue
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endfunction
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function ActionValue#(CsrReadResult#(xlen)) readWithOffset1(RVPrivilegeLevel privilegeLevel, RVCsrIndexOffset offset);
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actionvalue
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let csrReadResult <- readInternal(getIndex(privilegeLevel, offset));
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return csrReadResult;
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endactionvalue
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endfunction
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function ActionValue#(CsrWriteResult) writeWithOffset1(RVPrivilegeLevel privilegeLevel, RVCsrIndexOffset offset, Bit#(xlen) value);
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actionvalue
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let csrWriteResult <- writeInternal(getIndex(privilegeLevel, offset), value);
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return csrWriteResult;
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endactionvalue
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endfunction
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method Action incrementCycleCounters;
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cycleCounter.incr(1);
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timeCounter.incr(1);
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endmethod
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method Action incrementInstructionsRetiredCounter;
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retiredCounter.incr(1);
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endmethod
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//
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// CsrReadport
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//
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interface CsrReadPort csrReadPort;
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method ActionValue#(CsrReadResult#(xlen)) read(RVCsrIndex index);
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let result = CsrReadResult {
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value: 0,
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denied: True
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};
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if (currentPriv >= index[9:8]) begin
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result <- readInternal(index);
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end
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return result;
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endmethod
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endinterface
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//
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// CsrWritePort
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//
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interface CsrWritePort csrWritePort;
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method ActionValue#(CsrWriteResult) write(RVCsrIndex index, Bit#(xlen) value);
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let result = CsrWriteResult {
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denied: True
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};
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if (currentPriv >= index[9:8] && index[11:10] != 'b11) begin
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result <- writeInternal(index, value);
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end
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return result;
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endmethod
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endinterface
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//
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// CsrWritePermission
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//
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interface CsrWritePermission csrWritePermission;
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method Bool isWriteable(RVCsrIndex index);
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return (currentPriv >= index[9:8] && index[11:10] != 'b11);
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endmethod
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endinterface
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//
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// trapController
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//
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interface TrapController trapController;
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method ActionValue#(Bit#(xlen)) beginTrap(Bit#(xlen) trapProgramCounter, Trap#(xlen) trap);
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Bit#(xlen) cause = 0;
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let trapPrivilegeLevel = getTrapPrivilegeLevel(trap);
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/*
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cause = zeroExtend(trap.cause);
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if (!trap.isInterrupt) begin
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cause[valueOf(xlen)-1] = 1;
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end
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*/
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// PC => MEPC
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writeWithOffset1(trapPrivilegeLevel, csr_EPC, trapProgramCounter);
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// CurPriv => MSTATUS::MPP
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let mstatus_ <- mstatus.getMachineStatus.get;
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mstatus_.mpp = currentPriv;
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// MSTATUS::MIE => MSTATUS::MPIE
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mstatus_.mpie = mstatus_.mie;
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mstatus_.mie = False; // Disable interrupts
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mstatus.putMachineStatus.put(mstatus_);
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// cause => CAUSE
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writeWithOffset1(trapPrivilegeLevel, csr_CAUSE, cause);
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writeWithOffset1(trapPrivilegeLevel, csr_TVAL, trap.tval);
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let readResult <- readWithOffset1(trapPrivilegeLevel, csr_TVEC);
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Bit#(xlen) vectorTableBase = readResult.value;
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let trapHandler = vectorTableBase;
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// Check and handle a vectored trap handler table
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/*
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if (trapHandler[1:0] == 1) begin
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trapHandler[1:0] = 0;
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if(trap.isInterrupt) begin
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trapHandler = trapHandler + extend(4 * trap.cause);
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end
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end
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*/
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currentPriv <= trapPrivilegeLevel;
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return trapHandler;
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endmethod
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method ActionValue#(Bit#(xlen)) endTrap;
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Bit#(xlen) newProgramCounter = 'hDEADDEAD;
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let readStatus <- readWithOffset1(currentPriv, csr_STATUS);
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if (readStatus.denied == False) begin
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/*
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MachineStatus#(xlen) mstatus = unpack(readStatus.value);
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let newPrivilegeLevel = mstatus.mpp;
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mstatus.mie = mstatus.mpie;
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mstatus.mpie = False;
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*/
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// Attempt to update MSTATUS. The current privilege level may prevent this.
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/*
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let writeStatus <- writeInternal(csr_MSTATUS, pack(mstatus));
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if (writeStatus.denied == False) begin
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currentPriv <= newPrivilegeLevel;
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readStatus <- readWithOffset1(currentPriv, csr_EPC);
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if (readStatus.denied == False) begin
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newProgramCounter = readStatus.value;
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end
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end
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*/
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end
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return newProgramCounter;
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endmethod
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endinterface
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endmodule
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