diff --git a/src/Cpu/FetchStage.bsv b/src/Cpu/FetchStage.bsv
index 6334737..16d183d 100644
--- a/src/Cpu/FetchStage.bsv
+++ b/src/Cpu/FetchStage.bsv
@@ -10,15 +10,12 @@ import FIFOF::*;
 import GetPut::*;
 import Memory::*;
 
-typedef struct {
-} FetchStage_Cfg#(numeric type xlen);
-
 interface FetchStage_Ifc#(numeric type xlen);
     method ActionValue#(IF_ID#(xlen)) step(PC_IF#(xlen) pc_if);
     interface ReadOnlyMemoryClient#(xlen, 32) memoryClient;
 endinterface
 
-module mkFetchStage#(FetchStage_Cfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
+module mkFetchStage#(IsaCfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
     Reg#(Bool)          stall <- mkReg(False);
     Reg#(Bool)          externalStall <- mkReg(False);
 
diff --git a/src/Cpu/FetchStage_tb.bsv b/src/Cpu/FetchStage_tb.bsv
index 95048d8..299919c 100644
--- a/src/Cpu/FetchStage_tb.bsv
+++ b/src/Cpu/FetchStage_tb.bsv
@@ -15,16 +15,24 @@ module mkTopModule(Empty);
     Reg#(Bit#(20)) testNumber <- mkReg(0);
 
     // 32 bit
-    FetchStage_Cfg#(32) fetchStageConfig32 = FetchStage_Cfg{};
-    FetchStage_Ifc#(32) fetchStage32 <- mkFetchStage(fetchStageConfig32);
+    IsaCfg#(32) rv32 = IsaCfg{
+        extN: False,
+        extS: False,
+        extU: False
+    };
+    FetchStage_Ifc#(32) fetchStage32 <- mkFetchStage(rv32);
 
     FIFOF#(ReadOnlyMemoryRequest#(32)) memoryRequests32 <- mkUGFIFOF1();
 
     mkConnection(fetchStage32.memoryClient.request, toPut(asIfc(memoryRequests32)));
 
     // 64 bit
-    FetchStage_Cfg#(64) fetchStageConfig64 = FetchStage_Cfg{};
-    FetchStage_Ifc#(64) fetchStage64 <- mkFetchStage(fetchStageConfig64);
+    IsaCfg#(64) rv64 = IsaCfg{
+        extN: False,
+        extS: False,
+        extU: False
+    };
+    FetchStage_Ifc#(64) fetchStage64 <- mkFetchStage(rv64);
 
     (* no_implicit_conditions *)
     rule test;