diff --git a/src/Cpu/MemoryAccessStage.bsv b/src/Cpu/MemoryAccessStage.bsv
index 4a8cbd9..c849d27 100644
--- a/src/Cpu/MemoryAccessStage.bsv
+++ b/src/Cpu/MemoryAccessStage.bsv
@@ -28,7 +28,11 @@ module mkMemoryAccessStage#(IsaCfg#(xlen) cfg)(MemoryAccessStage_Ifc#(xlen));
     //        responding to any responses that have returned.  If a request is in flight, a bubble is returned.
     //
     method ActionValue#(MEM_WB#(xlen)) step(EX_MEM#(xlen) ex_mem);
-        return defaultValue;
+        MEM_WB#(xlen) mem_wb = defaultValue;
+        if (!ex_mem.common.isBubble) begin
+        end
+        
+        return mem_wb;
     endmethod
 
     interface MemoryClient memoryClient;
diff --git a/src/Cpu/PipelineRegisters.bsv b/src/Cpu/PipelineRegisters.bsv
index 1cb65ea..ab97f46 100644
--- a/src/Cpu/PipelineRegisters.bsv
+++ b/src/Cpu/PipelineRegisters.bsv
@@ -71,7 +71,7 @@ typedef struct {
     Bit#(xlen)                    npc;         // Next program counter
     Bit#(xlen)                    a;           // Operand 1
     Bit#(xlen)                    b;           // Operand 2
-    Bool                          isBValid;   // In the case of a CSR, this will indicate if 'b' is valid 
+    Bool                          isBValid;    // In the case of a CSR, this will indicate if 'b' is valid 
     Bit#(xlen)                    imm;         // Sign extended immediate
 } ID_EX#(numeric type xlen) deriving(Bits, Eq, FShow);