PrettyGoodRISCV/E-Series
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This commit is contained in:
John Terrell 2023-04-25 16:45:58 -07:00
parent b82a6a9a79
commit 96b36317b3
Signed by untrusted user who does not match committer: johnt
GPG Key ID: 2E424258DD3731F4
2 changed files with 27 additions and 26 deletions
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15
src/Cpu/CSRs/MachineStatus.bsv
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@ -150,8 +150,8 @@ endinstance
interface MachineStatusIfc#(numeric type xlen);
method Action beginTrap(RVPrivilegeLevel currentPriv);
interface Get#(Bit#(xlen)) getMachineStatus;
interface Put#(Bit#(xlen)) putMachineStatus;
method Bit#(xlen) get;
method Action put(Bit#(xlen) newMachineStatus);
endinterface
module mkMachineStatus#(IsaCfg#(xlen) cfg)(MachineStatusIfc#(xlen))
@ -172,14 +172,16 @@ module mkMachineStatus#(IsaCfg#(xlen) cfg)(MachineStatusIfc#(xlen))
mstatus <= mstatus_pack(mstatus_);
endmethod
interface Get getMachineStatus = toGet(mstatus);
interface Put putMachineStatus;
method Action put(Bit#(xlen) newValue);
method Bit#(xlen) get;
return mstatus;
endmethod
method Action put(Bit#(xlen) newMachineStatus);
//
// Only MPP, MIE, and MIE are writable.
//
MachineStatus mstatus_ = mstatus_unpack(mstatus);
MachineStatus value = mstatus_unpack(newValue);
MachineStatus value = mstatus_unpack(newMachineStatus);
if (cfg.extS) begin
mstatus_.mpp = value.mpp;
@ -197,5 +199,4 @@ module mkMachineStatus#(IsaCfg#(xlen) cfg)(MachineStatusIfc#(xlen))
mstatus <= mstatus_pack(mstatus_);
endmethod
endinterface
endmodule

4
src/Cpu/CsrFile.bsv
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@ -180,7 +180,7 @@ module mkCsrFile#(IsaCfg#(xlen) cfg)(CsrFileIfc#(xlen))
csr_MIDELEG: result.value = mideleg;
csr_MEDELEG: result.value = medeleg;
csr_MSTATUS: result.value <- mstatus.getMachineStatus.get;
csr_MSTATUS: result.value = mstatus.get;
csr_MCYCLE, csr_CYCLE: begin
result.value = mcycle;
@ -226,7 +226,7 @@ module mkCsrFile#(IsaCfg#(xlen) cfg)(CsrFileIfc#(xlen))
// No-Op
end
csr_MSCRATCH: mscratch <= value;
csr_MSTATUS: mstatus.putMachineStatus.put(value);
csr_MSTATUS: mstatus.put(value);
csr_MTVAL: mtval <= value;
csr_MTVEC: mtvec <= value;
csr_MIE: mie <= value;