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This commit is contained in:
John Terrell 2023-04-23 11:18:03 -07:00
parent fda8dafad7
commit 73ae766dc1
Signed by untrusted user who does not match committer: johnt
GPG Key ID: 2E424258DD3731F4
11 changed files with 24 additions and 28 deletions
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4
src/Cpu/CSRs/MachineISA.bsv
View File

@ -67,13 +67,13 @@ instance DefaultValue#(MachineISA);
};
endinstance
interface MachineISA_Ifc#(numeric type xlen);
interface MachineISAIfc#(numeric type xlen);
method Bit#(xlen) pack;
interface Get#(MachineISA) getMachineISA;
interface Put#(MachineISA) putMachineISA;
endinterface
module mkMachineISA#(IsaCfg#(xlen) cfg)(MachineISA_Ifc#(xlen))
module mkMachineISA#(IsaCfg#(xlen) cfg)(MachineISAIfc#(xlen))
provisos(
Add#(a__, 26, xlen),
Add#(b__, 2, xlen)

4
src/Cpu/CSRs/MachineISA_tb.bsv
View File

@ -12,14 +12,14 @@ module mkTopModule(Empty);
extS: False,
extU: False
};
MachineISA_Ifc#(32) rv32i <- mkMachineISA(rv32i_cfg);
MachineISAIfc#(32) rv32i <- mkMachineISA(rv32i_cfg);
IsaCfg#(64) rv64i_cfg = IsaCfg {
extN: False,
extS: False,
extU: False
};
MachineISA_Ifc#(64) rv64i <- mkMachineISA(rv64i_cfg);
MachineISAIfc#(64) rv64i <- mkMachineISA(rv64i_cfg);
(* no_implicit_conditions *)
rule test;

4
src/Cpu/CSRs/MachineStatus.bsv
View File

@ -148,13 +148,13 @@ instance MachineStatusBits#(64);
endfunction
endinstance
interface MachineStatus_Ifc#(numeric type xlen);
interface MachineStatusIfc#(numeric type xlen);
method Action beginTrap(RVPrivilegeLevel currentPriv);
interface Get#(Bit#(xlen)) getMachineStatus;
interface Put#(Bit#(xlen)) putMachineStatus;
endinterface
module mkMachineStatus#(IsaCfg#(xlen) cfg)(MachineStatus_Ifc#(xlen))
module mkMachineStatus#(IsaCfg#(xlen) cfg)(MachineStatusIfc#(xlen))
provisos(
Add#(a__, 32, xlen),
MachineStatusBits#(xlen)

4
src/Cpu/CSRs/MachineStatus_tb.bsv
View File

@ -7,10 +7,10 @@ module mkTopModule(Empty);
Reg#(Bit#(20)) stepNumber <- mkReg(0);
IsaCfg#(32) rv32icfg = defaultValue;
MachineStatus_Ifc#(32) rv32i <- mkMachineStatus(rv32icfg);
MachineStatusIfc#(32) rv32i <- mkMachineStatus(rv32icfg);
IsaCfg#(64) rv64icfg = defaultValue;
MachineStatus_Ifc#(64) rv64i <- mkMachineStatus(rv64icfg);
MachineStatusIfc#(64) rv64i <- mkMachineStatus(rv64icfg);
(* no_implicit_conditions *)
rule test;

18
src/Cpu/CsrFile.bsv
View File

@ -30,7 +30,7 @@ interface CsrWritePermission;
method Bool isWriteable(RVCSRIndex index);
endinterface
interface CsrFile#(numeric type xlen);
interface CsrFileIfc#(numeric type xlen);
method Action incrementCycleCounters;
method Action incrementInstructionsRetiredCounter;
@ -41,11 +41,7 @@ interface CsrFile#(numeric type xlen);
interface TrapController#(xlen) trapController;
endinterface
typedef struct {
IsaCfg#(xlen) isa_cfg;
} CsrFileCfg#(numeric type xlen);
module mkCsrFile#(CsrFileCfg#(xlen) cfg)(CsrFile#(xlen))
module mkCsrFile#(IsaCfg#(xlen) cfg)(CsrFileIfc#(xlen))
provisos(
Add#(xlen, 0, 32),
Add#(xlen, 0, 64)
@ -68,8 +64,8 @@ module mkCsrFile#(CsrFileCfg#(xlen) cfg)(CsrFile#(xlen))
mconfigptr: 0
};
MachineStatus_Ifc#(xlen) mstatus <- mkMachineStatus(cfg.isa_cfg);
MachineISA_Ifc#(xlen) misa <- mkMachineISA(cfg.isa_cfg);
MachineStatusIfc#(xlen) mstatus <- mkMachineStatus(cfg);
MachineISAIfc#(xlen) misa <- mkMachineISA(cfg);
ReadOnly#(Bit#(xlen)) mcycle <- mkReadOnly(truncate(cycleCounter));
ReadOnly#(Bit#(xlen)) mtimer <- mkReadOnly(truncate(timeCounter));
ReadOnly#(Bit#(xlen)) minstret <- mkReadOnly(truncate(retiredCounter));
@ -118,7 +114,7 @@ module mkCsrFile#(CsrFileCfg#(xlen) cfg)(CsrFile#(xlen))
let trap_privilege_level = priv_MACHINE;
if (currentPriv < priv_MACHINE) begin
if (cfg.isa_cfg.extS) begin // S mode supported?
if (cfg.extS) begin // S mode supported?
// See if this trap should be delegated to SUPERVISOR mode
let delegated = (trap.isInterrupt ?
(mideleg[trap.cause] == 0 ? False : True) :
@ -129,7 +125,7 @@ module mkCsrFile#(CsrFileCfg#(xlen) cfg)(CsrFile#(xlen))
// If the current priv mode is U, and user mode traps are supported,
// then consult sedeleg/sideleg to determine if delegated to USER mode.
if (currentPriv == priv_USER && cfg.isa_cfg.extU) begin
if (currentPriv == priv_USER && cfg.extU) begin
delegated = (trap.isInterrupt ?
(sideleg[trap.cause] == 0 ? False : True) :
(sedeleg[trap.cause] == 0 ? False : True));
@ -142,7 +138,7 @@ module mkCsrFile#(CsrFileCfg#(xlen) cfg)(CsrFile#(xlen))
end else begin // S mode *NOT* supported
// If user mode traps are supported, then consult sedeleg/sideleg to determine
// if delegated to USER mode.
if (cfg.isa_cfg.extU) begin
if (cfg.extU) begin
let delegated = (trap.isInterrupt ?
(mideleg[trap.cause] == 0 ? False : True) :
(medeleg[trap.cause] == 0 ? False : True));

4
src/Cpu/DecodeStage.bsv
View File

@ -5,7 +5,7 @@ import PipelineRegisters::*;
import RV_ISA::*;
import Trap::*;
interface DecodeStage_Ifc#(numeric type xlen);
interface DecodeStageIfc#(numeric type xlen);
method ActionValue#(ID_EX#(xlen)) step(
IF_ID#(xlen) if_id,
GprReadPort#(xlen) gprReadPort1,
@ -14,7 +14,7 @@ interface DecodeStage_Ifc#(numeric type xlen);
);
endinterface
module mkDecodeStage#(IsaCfg#(xlen) cfg)(DecodeStage_Ifc#(xlen))
module mkDecodeStage#(IsaCfg#(xlen) cfg)(DecodeStageIfc#(xlen))
provisos(
Add#(a__, 20, xlen),
Add#(b__, 5, xlen),

2
src/Cpu/DecodeStage_tb.bsv
View File

@ -16,7 +16,7 @@ module mkTopModule(Empty);
extS: False,
extU: False
};
DecodeStage_Ifc#(32) decodeStage32 <- mkDecodeStage(rv32);
DecodeStageIfc#(32) decodeStage32 <- mkDecodeStage(rv32);
//
// GPR

4
src/Cpu/FetchStage.bsv
View File

@ -10,13 +10,13 @@ import FIFOF::*;
import GetPut::*;
import Memory::*;
interface FetchStage_Ifc#(numeric type xlen);
interface FetchStageIfc#(numeric type xlen);
method ActionValue#(IF_ID#(xlen)) step(PC_IF#(xlen) pc_if);
interface ReadOnlyMemoryClient#(xlen, 32) memoryClient;
endinterface
module mkFetchStage#(IsaCfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
module mkFetchStage#(IsaCfg#(xlen) cfg)(FetchStageIfc#(xlen));
Reg#(ProgramCounter#(xlen)) updatedPc <- mkRegU; // Holds the updated PC that is calculated when a fetch is issued
// that is used to update the PC when the fetch completes.

2
src/Cpu/FetchStage_tb.bsv
View File

@ -20,7 +20,7 @@ module mkTopModule(Empty);
extS: False,
extU: False
};
FetchStage_Ifc#(32) fetchStage32 <- mkFetchStage(rv32);
FetchStageIfc#(32) fetchStage32 <- mkFetchStage(rv32);
FIFOF#(ReadOnlyMemoryRequest#(32)) memoryRequests32 <- mkUGFIFOF1();
mkConnection(fetchStage32.memoryClient.request, toPut(asIfc(memoryRequests32)));

4
src/Cpu/MemoryAccessStage.bsv
View File

@ -9,12 +9,12 @@ import FIFOF::*;
import GetPut::*;
import Memory::*;
interface MemoryAccessStage_Ifc#(numeric type xlen);
interface MemoryAccessStageIfc#(numeric type xlen);
method ActionValue#(MEM_WB#(xlen)) step(EX_MEM#(xlen) ex_mem);
interface MemoryClient#(xlen, xlen) memoryClient;
endinterface
module mkMemoryAccessStage#(IsaCfg#(xlen) cfg)(MemoryAccessStage_Ifc#(xlen));
module mkMemoryAccessStage#(IsaCfg#(xlen) cfg)(MemoryAccessStageIfc#(xlen));
// Memory request output
Reg#(Bool) memoryRequestInFlight <- mkReg(False);
Wire#(MemoryRequest#(xlen, xlen)) memoryRequest <- mkWire;

2
src/Cpu/MemoryAccessStage_tb.bsv
View File

@ -20,7 +20,7 @@ module mkTopModule(Empty);
extS: False,
extU: False
};
MemoryAccessStage_Ifc#(32) memoryAccessStage32 <- mkMemoryAccessStage(rv32);
MemoryAccessStageIfc#(32) memoryAccessStage32 <- mkMemoryAccessStage(rv32);
FIFOF#(MemoryRequest#(32, 32)) memoryRequests32 <- mkUGFIFOF1();