FetchStage fixups and tests.
This commit is contained in:
John Terrell
parent
4d9aa3063c
commit
5e1448d1d6
GPG Key ID:
2E424258DD3731F4
@ -4,29 +4,21 @@ import PipelineRegisters::*;
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import RV_ISA::*;
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import Trap::*;
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import Assert::*;
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import ClientServer::*;
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import FIFOF::*;
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import GetPut::*;
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import Memory::*;
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import RWire::*;
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typedef struct {
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} FetchStage_Cfg#(numeric type xlen);
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interface FetchStage_Ifc#(numeric type xlen);
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interface Put#(PC_IF#(xlen)) putPC_IF;
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interface Get#(IF_ID#(xlen)) getIF_ID;
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method ActionValue#(IF_ID#(xlen)) step(PC_IF#(xlen) pc_if);
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interface ReadOnlyMemoryClient#(xlen, 32) memoryClient;
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interface Get#(Bit#(xlen)) getNPC;
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interface Put#(Bool) putStall;
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endinterface
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module mkFetchStage#(FetchStage_Cfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
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Wire#(PC_IF#(xlen)) pc_if <- mkWire;
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Wire#(IF_ID#(xlen)) if_id <- mkWire;
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Wire#(Bit#(xlen)) npc <- mkWire;
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Reg#(Bool) stall <- mkReg(False);
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Reg#(Bool) externalStall <- mkReg(False);
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@ -35,21 +27,23 @@ module mkFetchStage#(FetchStage_Cfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
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Wire#(ReadOnlyMemoryRequest#(xlen)) memoryRequest <- mkWire;
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// Memory response input (FIFO)
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FIFOF#(ReadOnlyMemoryResponse#(32)) memoryResponses <- mkFIFOF;
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// Note: This is an unguarded FIFO so status much be checked before attempting to enq() and deq().
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FIFOF#(ReadOnlyMemoryResponse#(32)) memoryResponses <- mkUGFIFOF1;
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//
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// processMemoryResponse - takes a memory response and returns an IF_ID containing
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// the encoded instruction (or a trap if the original request
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// was denied by the memory system)
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//
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function IF_ID#(xlen) processMemoryResponse(ReadOnlyMemoryResponse#(32) response);
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IF_ID#(xlen) if_id_ = defaultValue;
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if_id_.common.pc = pc_if.common.pc;
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if_id_.common.isBubble = False;
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function IF_ID#(xlen) processMemoryResponse(PC_IF#(xlen) pc_if, ReadOnlyMemoryResponse#(32) response);
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IF_ID#(xlen) if_id = defaultValue;
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if_id.common.pc = pc_if.pc;
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if_id.common.isBubble = False;
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if_id.npc = pc_if.pc + 4;
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if (!response.accessFault) begin
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if_id_.common.ir = response.data;
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if_id_.common.trap = tagged Invalid;
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if_id.common.ir.value = response.data;
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if_id.common.trap = tagged Invalid;
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end else begin
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Trap#(xlen) trap = Trap {
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cause: exception_INSTRUCTION_ACCESS_FAULT,
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@ -57,23 +51,18 @@ module mkFetchStage#(FetchStage_Cfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
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tval: 0
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};
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if_id_.common.trap = tagged Valid(trap);
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if_id.common.trap = tagged Valid(trap);
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end
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return if_id_;
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return if_id;
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endfunction
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rule fetch;
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IF_ID#(xlen) if_id_ = defaultValue;
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if_id_.common.pc = pc_if.common.pc;
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if_id_.common.isBubble = True;
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npc <= pc_if.common.pc + 4;
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if (!pc_if.common.isBubble && !stall) begin
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method ActionValue#(IF_ID#(xlen)) step(PC_IF#(xlen) pc_if);
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IF_ID#(xlen) if_id = defaultValue;
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if (!pc_if.isBubble) begin
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// If there's an active request, handle it if it's returned
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if (memoryRequestInFlight) begin
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if (memoryResponses.notEmpty) begin
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if_id_ = processMemoryResponse(memoryResponses.first);
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if_id = processMemoryResponse(pc_if, memoryResponses.first);
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memoryResponses.deq;
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memoryRequestInFlight <= False;
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end else begin
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@ -83,37 +72,37 @@ module mkFetchStage#(FetchStage_Cfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
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// No memory request is in flight...
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// Check for a misaligned request
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if (pc_if.common.pc[1:0] != 0) begin
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if (pc_if.pc[1:0] != 0) begin
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// Address request was misaligned...
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Trap#(xlen) trap = Trap {
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cause: exception_INSTRUCTION_ADDRESS_MISALIGNED,
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isInterrupt: False,
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tval: 0
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};
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if_id_.common.trap = tagged Valid(trap);
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if_id_.common.isBubble = False;
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if_id.common.pc = pc_if.pc;
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if_id.common.trap = tagged Valid(trap);
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if_id.common.isBubble = False;
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end else begin
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// Construct a memory request and send it out.
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ReadOnlyMemoryRequest#(xlen) request = ReadOnlyMemoryRequest {
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address: pc_if.common.pc
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address: pc_if.pc
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};
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memoryRequest <= request;
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memoryRequestInFlight <= True;
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if_id_.common.isBubble = True;
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end
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end
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end
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// Determine if fetching should stall on the next cycle.
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stall <= externalStall; // || ichache_miss || itlb_busy;
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return if_id;
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endmethod
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if_id <= if_id_;
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endrule
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interface Put putPC_IF = toPut(asIfc(pc_if));
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interface Get getIF_ID = toGet(if_id);
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interface ReadOnlyMemoryClient memoryClient = toGPClient(memoryRequest, memoryResponses);
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interface Get getNPC = toGet(npc);
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interface Put putStall = toPut(asIfc(externalStall));
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interface ReadOnlyMemoryClient memoryClient;
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interface Get request = toGet(memoryRequest);
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interface Put response;
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method Action put(ReadOnlyMemoryResponse#(32) response);
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dynamicAssert(memoryResponses.notFull, "FetchStage - attempt to put a memory respnose on a full queue");
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memoryResponses.enq(response);
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endmethod
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endinterface
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endinterface
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endmodule
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@ -1,35 +1,107 @@
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import FetchStage::*;
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import IsaCfg::*;
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import MemoryTypes::*;
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import PipelineRegisters::*;
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import RV_ISA::*;
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import Trap::*;
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import Assert::*;
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import ClientServer::*;
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import Connectable::*;
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import FIFOF::*;
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import GetPut::*;
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module mkTopModule(Empty);
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Reg#(Bit#(20)) testNumber <- mkReg(0);
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// 32 bit
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FetchStage_Cfg#(32) fetchStageConfig32 = FetchStage_Cfg{};
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FetchStage_Ifc#(32) fetchStage32 <- mkFetchStage(fetchStageConfig32);
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Wire#(PC_IF#(32)) pc_if32 <- mkWire;
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Wire#(IF_ID#(32)) if_id32 <- mkWire;
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FIFOF#(ReadOnlyMemoryRequest#(32)) memoryRequests32 <- mkUGFIFOF1();
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mkConnection(toGet(pc_if32), fetchStage32.putPC_IF);
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mkConnection(fetchStage32.getIF_ID, toPut(asIfc(if_id32)));
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mkConnection(fetchStage32.memoryClient.request, toPut(asIfc(memoryRequests32)));
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// 64 bit
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FetchStage_Cfg#(64) fetchStageConfig64 = FetchStage_Cfg{};
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FetchStage_Ifc#(64) fetchStage64 <- mkFetchStage(fetchStageConfig64);
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Wire#(PC_IF#(64)) pc_if64 <- mkWire;
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Wire#(IF_ID#(64)) if_id64 <- mkWire;
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mkConnection(toGet(pc_if64), fetchStage64.putPC_IF);
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mkConnection(fetchStage64.getIF_ID, toPut(asIfc(if_id64)));
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(* no_implicit_conditions *)
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rule test;
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//pc_if32 <= defaultValue;
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PC_IF#(32) pc_if = defaultValue;
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case(testNumber)
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// Simple bubble passthrough
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0: begin
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let if_id <- fetchStage32.step(pc_if);
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dynamicAssert(if_id == defaultValue, "Fetch - Bubble passthrough check");
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end
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// Misaligned instruction trap
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1: begin
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pc_if.pc = 'h101;
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pc_if.isBubble = False;
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let if_id <- fetchStage32.step(pc_if);
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dynamicAssert(if_id.common.pc == pc_if.pc, "Fetch - Misaligned instruction trap check - common.pc");
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dynamicAssert(if_id.common.ir == defaultValue, "Fetch - Misaligned instruction trap check - common.ir");
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dynamicAssert(!if_id.common.isBubble, "Fetch - Misaligned instruction trap check - common.isBubble");
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dynamicAssert(isValid(if_id.common.trap), "Fetch - Misaligned instruction trap check - contains trap");
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dynamicAssert(if_id.common.trap.Valid.cause == exception_INSTRUCTION_ADDRESS_MISALIGNED, "Fetch - Misaligned instruction trap check - cause is misaligned address");
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end
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// Memory request denied trap (request submit)
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2: begin
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pc_if.pc = 'h100;
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pc_if.isBubble = False;
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// The fetch should proceed and return a bubble.
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let if_id <- fetchStage32.step(pc_if);
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dynamicAssert(if_id == defaultValue, "Fetch - Memory request denied trap check - request should return a bubble");
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end
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// Memory request denied trap (request receipt)
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3: begin
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pc_if.pc = 'h100;
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pc_if.isBubble = False;
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// The fetch return a bubble while the memory request is in flight
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let if_id <- fetchStage32.step(pc_if);
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dynamicAssert(if_id == defaultValue, "Fetch - Memory request denied trap check - request should return a bubble while fetch is in flight");
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dynamicAssert(memoryRequests32.notEmpty, "Fetch - Memory request denied trap check - memory request queue should not be empty");
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let memoryRequest = memoryRequests32.first;
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memoryRequests32.deq;
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dynamicAssert(memoryRequest.address == 'h100, "Fetch - Memory request denied trap check - memory request should have correct address");
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fetchStage32.memoryClient.response.put(ReadOnlyMemoryResponse {
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data: 'h-1,
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accessFault: True
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});
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end
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// Memory request denied trap (return trap check)
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4: begin
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pc_if.pc = 'h100;
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pc_if.isBubble = False;
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// The fetch should proceed and return a bubble.
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let if_id <- fetchStage32.step(pc_if);
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dynamicAssert(if_id.common.pc == pc_if.pc, "Fetch - Memory request denied trap check - common.pc");
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dynamicAssert(if_id.common.ir == defaultValue, "Fetch - Memory request denied trap check - common.ir");
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dynamicAssert(!if_id.common.isBubble, "Fetch - Memory request denied trap check - common.isBubble");
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dynamicAssert(isValid(if_id.common.trap), "Fetch - Memory request denied trap check - contains trap");
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dynamicAssert(if_id.common.trap.Valid.cause == exception_INSTRUCTION_ACCESS_FAULT, "Memory request denied trap check - cause is access fault");
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end
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default: begin
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$display(">>>PASS");
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$finish();
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end
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endcase
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endrule
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rule increment_test_number;
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testNumber <= testNumber + 1;
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endrule
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endmodule
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@ -1,11 +1,21 @@
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import Trap::*;
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import DefaultValue::*;
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typedef struct {
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Bit#(32) value;
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} Instruction deriving(Bits, Eq, FShow);
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instance DefaultValue #(Instruction);
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defaultValue = Instruction {
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value: 32'b0000000_00000_00000_000_00000_0110011 // ADD x0, x0, x0
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};
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endinstance
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//
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// PipelineRegisterCommon
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//
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typedef struct {
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Bit#(32) ir;
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Instruction ir;
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Bit#(xlen) pc;
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Bool isBubble;
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Maybe#(Trap#(xlen)) trap;
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@ -13,8 +23,8 @@ typedef struct {
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instance DefaultValue #(PipelineRegisterCommon#(xlen));
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defaultValue = PipelineRegisterCommon {
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ir: 32'b0000000_00000_00000_000_00000_0110011, // ADD x0, x0, x0
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pc: 'hf000c0de,
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ir: defaultValue,
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pc: 'h-1,
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isBubble: True,
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trap: tagged Invalid
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};
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@ -24,12 +34,14 @@ endinstance
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// PC_IF
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//
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typedef struct {
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PipelineRegisterCommon#(xlen) common;
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Bit#(xlen) pc;
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Bool isBubble;
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} PC_IF#(numeric type xlen) deriving(Bits, Eq, FShow);
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instance DefaultValue #(PC_IF#(xlen));
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defaultValue = PC_IF {
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common: defaultValue
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pc: 'h-1,
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isBubble: True
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};
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endinstance
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@ -45,8 +57,8 @@ typedef struct {
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instance DefaultValue #(IF_ID#(xlen));
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defaultValue = IF_ID {
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common: defaultValue,
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epoch: 0,
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npc: 'hbeefbeef
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epoch: 'h-1,
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npc: 'h-1
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};
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endinstance
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@ -67,11 +79,11 @@ instance DefaultValue #(ID_EX#(xlen));
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defaultValue = ID_EX {
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common: defaultValue,
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epoch: 0,
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npc: 'hbeefbeef,
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a: 0,
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b: 0,
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npc: 'h-1,
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a: 'h-1,
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b: 'h-1,
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isBValid: True,
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imm: 0
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imm: 'h-1
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};
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endinstance
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@ -88,8 +100,8 @@ typedef struct {
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instance DefaultValue #(EX_MEM#(xlen));
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defaultValue = EX_MEM {
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common: defaultValue,
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aluOutput: 0,
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storeValueOrCSRWriteback: 0,
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aluOutput: 'h-1,
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storeValueOrCSRWriteback: 'h-1,
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cond: False
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};
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endinstance
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@ -106,8 +118,8 @@ typedef struct {
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instance DefaultValue #(MEM_WB#(xlen));
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defaultValue = MEM_WB {
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common: defaultValue,
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gprWritebackValue: 0,
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csrWritebackValue: 0
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gprWritebackValue: 'h-1,
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csrWritebackValue: 'h-1
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};
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endinstance
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@ -123,7 +135,7 @@ typedef struct {
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instance DefaultValue#(WB_OUT#(xlen));
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defaultValue = WB_OUT {
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common: defaultValue,
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gpr_writeback_value: 0,
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csr_writeback_value: 0
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gpr_writeback_value: 'h-1,
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csr_writeback_value: 'h-1
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};
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endinstance
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