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@ -18,11 +18,17 @@ interface FetchStage_Ifc#(numeric type xlen);
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interface Get#(IF_ID#(xlen)) getIF_ID;
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interface ReadOnlyMemoryClient#(xlen, 32) memoryClient;
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interface Get#(Bit#(xlen)) getNPC;
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interface Put#(Bool) putStall;
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endinterface
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module mkFetchStage#(FetchStage_Cfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
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Wire#(PC_IF#(xlen)) pc_if <- mkWire;
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Wire#(IF_ID#(xlen)) if_id <- mkWire;
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Wire#(Bit#(xlen)) npc <- mkWire;
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Reg#(Bool) stall <- mkReg(False);
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Reg#(Bool) externalStall <- mkReg(False);
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// Memory request output
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Reg#(Bool) memoryRequestInFlight <- mkReg(False);
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@ -31,6 +37,11 @@ module mkFetchStage#(FetchStage_Cfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
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// Memory response input (FIFO)
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FIFOF#(ReadOnlyMemoryResponse#(32)) memoryResponses <- mkFIFOF;
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//
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// processMemoryResponse - takes a memory response and returns an IF_ID containing
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// the encoded instruction (or a trap if the original request
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// was denied by the memory system)
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//
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function IF_ID#(xlen) processMemoryResponse(ReadOnlyMemoryResponse#(32) response);
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IF_ID#(xlen) if_id_ = defaultValue;
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if_id_.common.pc = pc_if.common.pc;
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@ -56,7 +67,9 @@ module mkFetchStage#(FetchStage_Cfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
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if_id_.common.pc = pc_if.common.pc;
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if_id_.common.isBubble = True;
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if (!pc_if.common.isBubble) begin
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npc <= pc_if.common.pc + 4;
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if (!pc_if.common.isBubble && !stall) begin
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// If there's an active request, handle it if it's returned
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if (memoryRequestInFlight) begin
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if (memoryResponses.notEmpty) begin
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@ -92,10 +105,15 @@ module mkFetchStage#(FetchStage_Cfg#(xlen) cfg)(FetchStage_Ifc#(xlen));
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end
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end
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// Determine if fetching should stall on the next cycle.
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stall <= externalStall; // || ichache_miss || itlb_busy;
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if_id <= if_id_;
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endrule
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interface Put putPC_IF = toPut(asIfc(pc_if));
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interface Get getIF_ID = toGet(if_id);
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interface ReadOnlyMemoryClient memoryClient = toGPClient(memoryRequest, memoryResponses);
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interface Get getNPC = toGet(npc);
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interface Put putStall = toPut(asIfc(externalStall));
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endmodule
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