Initial skeleton
This commit is contained in:
John Terrell
commit
0df29d8284
GPG Key ID:
2E424258DD3731F4
1
.gitignore
vendored
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1
.gitignore
vendored
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@ -0,0 +1 @@
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**/target
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3
dolly.toml
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3
dolly.toml
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[package]
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name = "ESeries"
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version = "0.1.0"
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116
src/Cpu/Alu.bsv
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116
src/Cpu/Alu.bsv
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//
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// ALU
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//
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// This module is a Arithmetic Logic Unit (ALU) implementation for RISC-V. It is
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// reponsible for mathematical operations inside the CPU.
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//
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import RV_ISA::*;
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export RV_ISA::*, AluCfg, AluIfc(..), mkAlu;
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typedef struct {
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} AluCfg#(numeric type xlen);
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interface AluIfc#(numeric type xlen);
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method Maybe#(Bit#(xlen)) execute(RVALUOperator operator, Bit#(xlen) operand1, Bit#(xlen) operand2);
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endinterface
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module mkAlu#(AluCfg#(xlen) cfg)(AluIfc#(xlen));
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method Maybe#(Bit#(xlen)) execute(RVALUOperator operator, Bit#(xlen) operand1, Bit#(xlen) operand2);
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let sum = operand1 + operand2;
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let difference = operand1 - operand2;
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let bitwise_and = operand1 & operand2;
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let bitwise_or = operand1 | operand2;
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let bitwise_xor = operand1 ^ operand2;
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let sltu = (operand1 < operand2 ? 1 : 0);
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let slt = (begin
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Int#(xlen) signedOperand1 = unpack(pack(operand1));
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Int#(xlen) signedOperand2 = unpack(pack(operand2));
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(signedOperand1 < signedOperand2 ? 1 : 0);
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end);
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Maybe#(Bit#(xlen)) result = ?;
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if (valueOf(xlen) == 32) begin
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let sll = operand1 << operand2[4:0];
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let sra = signedShiftRight(operand1, operand2[4:0]);
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let srl = operand1 >> operand2[4:0];
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result = case(operator)
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alu_ADD: tagged Valid sum;
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alu_SUB: tagged Valid difference;
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alu_AND: tagged Valid bitwise_and;
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alu_OR: tagged Valid bitwise_or;
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alu_XOR: tagged Valid bitwise_xor;
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alu_SLTU: tagged Valid sltu;
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alu_SLT: tagged Valid slt;
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alu_SLL: tagged Valid sll;
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alu_SRA: tagged Valid sra;
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alu_SRL: tagged Valid srl;
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default: tagged Invalid;
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endcase;
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end else if (valueOf(xlen) == 64) begin
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let sll = operand1 << operand2[5:0];
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let sra = signedShiftRight(operand1, operand2[5:0]);
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let srl = operand1 >> operand2[5:0];
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result = case(operator)
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alu_ADD: tagged Valid sum;
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alu_SUB: tagged Valid difference;
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alu_AND: tagged Valid bitwise_and;
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alu_OR: tagged Valid bitwise_or;
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alu_XOR: tagged Valid bitwise_xor;
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alu_SLTU: tagged Valid sltu;
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alu_SLT: tagged Valid slt;
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alu_SLL: tagged Valid sll;
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alu_SRA: tagged Valid sra;
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alu_SRL: tagged Valid srl;
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default: tagged Invalid;
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endcase;
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end
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return result;
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// return case(operator)
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// alu_ADD: tagged Valid (operand1 + operand2);
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// alu_SUB: tagged Valid (operand1 - operand2);
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// alu_AND: tagged Valid (operand1 & operand2);
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// alu_OR: tagged Valid (operand1 | operand2);
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// alu_XOR: tagged Valid (operand1 ^ operand2);
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// alu_SLTU: tagged Valid setLessThanUnsigned(operand1, operand2);
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// alu_SLT: tagged Valid setLessThan(operand1, operand2);
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// alu_SLL: (xlen == 32 ? tagged Valid (operand1 << operand2[4:0]) : tagged Invalid);
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// alu_SRA: (xlen == 32 ? tagged Valid signedShiftRight(operand1, operand2[4:0]) : tagged Invalid);
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// alu_SRL: (xlen == 32 ? tagged Valid (operand1 >> operand2[4:0]) : tagged Invalid);
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// end else if (xlen == 64) begin
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// alu_SLL: tagged Valid (operand1 << operand2[5:0]);
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// alu_SRA: tagged Valid signedShiftRight(operand1, operand2[5:0]);
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// alu_SRL: tagged Valid (operand1 >> operand2[5:0]);
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// alu_ADD32: begin
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// let result = operand1[31:0] + operand2[31:0];
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// return tagged Valid signExtend(result[31:0]);
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// end
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// alu_SUB32: begin
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// let result = (operand1[31:0] - operand2[31:0]);
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// return tagged Valid signExtend(result[31:0]);
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// end
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// alu_SLL32: begin
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// let result = (operand1[31:0] << operand2[4:0]);
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// return tagged Valid signExtend(result[31:0]);
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// end
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// alu_SRA32: begin
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// let result = signedShiftRight(operand1[31:0], operand2[4:0]);
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// return tagged Valid signExtend(result[31:0]);
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// end
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// alu_SRL32: begin
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// let result = (operand1[31:0] >> operand2[4:0]);
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// return tagged Valid signExtend(result[31:0]);
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// end
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// end
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// default: tagged Invalid;
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// endcase;
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endmethod
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endmodule
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23
src/Cpu/Cpu.bsv
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23
src/Cpu/Cpu.bsv
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import ALU::*;
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//
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// CpuConfig
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//
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typedef struct {
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} CpuCfg#(numeric type xlen);
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//
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// CpuIfc
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//
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interface CpuIfc#(type cfg);
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endinterface
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//
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// mkCpu()
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//
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module mkCpu#(CpuCfg#(xlen) cfg)(CpuIfc#(cfg));
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AluCfg#(xlen) alu_cfg = AluCfg {};
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let alu <- mkAlu(alu_cfg);
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endmodule
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export CpuCfg(..), CpuIfc, mkCpu;
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296
src/Cpu/RV_ISA.bsv
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296
src/Cpu/RV_ISA.bsv
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typedef Bit#(3) RVFunc3; // Corresponds to the func3 instruction field.
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//
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// RVALUOperator
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//
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typedef Bit#(11) RVALUOperator;
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// ALU Operators: These are decoded as the concat of a single bit indicating if a 6432 operation and func7 and func3
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RVALUOperator alu_ADD = 11'b0_0000000_000;
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RVALUOperator alu_SLL = 11'b0_0000000_001;
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RVALUOperator alu_SLT = 11'b0_0000000_010;
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RVALUOperator alu_SLTU = 11'b0_0000000_011;
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RVALUOperator alu_XOR = 11'b0_0000000_100;
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RVALUOperator alu_SRL = 11'b0_0000000_101;
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RVALUOperator alu_OR = 11'b0_0000000_110;
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RVALUOperator alu_AND = 11'b0_0000000_111;
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RVALUOperator alu_MUL = 11'b0_0000001_000;
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RVALUOperator alu_MULH = 11'b0_0000001_001;
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RVALUOperator alu_MULHSU = 11'b0_0000001_010;
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RVALUOperator alu_MULHU = 11'b0_0000001_011;
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RVALUOperator alu_DIV = 11'b0_0000001_100;
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RVALUOperator alu_DIVU = 11'b0_0000001_101;
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RVALUOperator alu_REM = 11'b0_0000001_110;
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RVALUOperator alu_REMU = 11'b0_0000001_111;
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RVALUOperator alu_SUB = 11'b0_0100000_000;
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RVALUOperator alu_SRA = 11'b0_0100000_101;
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RVALUOperator alu_ADD32 = 11'b1_0000000_000;
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RVALUOperator alu_SLL32 = 11'b1_0000000_001;
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RVALUOperator alu_SRL32 = 11'b1_0000000_101;
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RVALUOperator alu_SUB32 = 11'b1_0100000_000;
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RVALUOperator alu_SRA32 = 11'b1_0100000_101;
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//
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// RVBranchOperator(s)
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//
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typedef RVFunc3 RVBranchOperator;
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RVBranchOperator branch_BEQ = 3'b000;
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RVBranchOperator branch_BNE = 3'b001;
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RVBranchOperator branch_UNSUPPORTED_010 = 3'b010;
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RVBranchOperator branch_UNSUPPORTED_011 = 3'b011;
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RVBranchOperator branch_BLT = 3'b100;
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RVBranchOperator branch_BGE = 3'b101;
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RVBranchOperator branch_BLTU = 3'b110;
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RVBranchOperator branch_BGEU = 3'b111;
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//
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// RVCSRIndex
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//
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typedef Bit#(12) RVCSRIndex;
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// Supervisor Trap Setup
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RVCSRIndex csr_SSTATUS = 12'h100; // Supervisor Status Register (SRW)
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RVCSRIndex csr_SIE = 12'h104; // Supervisor Interrupt Enable Register (SRW)
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RVCSRIndex csr_STVEC = 12'h105; // Supervisor Trap-Handler base address (SRW)
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RVCSRIndex csr_SCOUNTEREN = 12'h106; // Supervisor Counter Enable Register (SRW)
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// Supervisor Configuration
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RVCSRIndex csr_SENVCFG = 12'h10A; // Supervisor environment configuration register (SRW)
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// Supervisor Trap Handling
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RVCSRIndex csr_SSCRATCH = 12'h140; // Scratch register for supervisor trap handlers (SRW)
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RVCSRIndex csr_SEPC = 12'h141; // Supervisor exception program counter (SRW)
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RVCSRIndex csr_SCAUSE = 12'h142; // Supervisor trap cause (SRW)
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RVCSRIndex csr_STVAL = 12'h143; // Supervisor bad address or instruction (SRW)
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RVCSRIndex csr_SIP = 12'h144; // Supervisor interrupt pending (SRW)
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// Supervisor Protection and Translation
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RVCSRIndex csr_SATP = 12'h180; // Supervisor address translation and protection (SRW)
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// Machine Trap Setup
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RVCSRIndex csr_MSTATUS = 12'h300; // Machine Status Register (MRW)
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RVCSRIndex csr_MISA = 12'h301; // Machine ISA and Extensions Register (MRW)
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RVCSRIndex csr_MEDELEG = 12'h302; // Machine Exception Delegation Register (MRW)
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RVCSRIndex csr_MIDELEG = 12'h303; // Machine Interrupt Delegation Register (MRW)
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RVCSRIndex csr_MIE = 12'h304; // Machine Interrupt Enable Register (MRW)
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RVCSRIndex csr_MTVEC = 12'h305; // Machine Trap-Handler base address (MRW)
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RVCSRIndex csr_MCOUNTEREN = 12'h306; // Machine Counter Enable Register (MRW)
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`ifdef RV32
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RVCSRIndex csr_MSTATUSH = 12'h310; // Additional machine status register, RV32 only (MRW)
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`endif
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// Machine Trap Handling
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RVCSRIndex csr_MSCRATCH = 12'h340; // Scratch register for machine trap handlers (MRW)
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RVCSRIndex csr_MEPC = 12'h341; // Machine exception program counter (MRW)
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RVCSRIndex csr_MCAUSE = 12'h342; // Machine trap cause (MRW)
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RVCSRIndex csr_MTVAL = 12'h343; // Machine bad address or instruction (MRW)
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RVCSRIndex csr_MIP = 12'h344; // Machine interrupt pending (MRW)
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RVCSRIndex csr_MTINST = 12'h34A; // Machine trap instruction (transformed) (MRW)
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RVCSRIndex csr_MTVAL2 = 12'h34B; // Machine bad guest physical address (MRW)
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// Machine Memory Protection
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RVCSRIndex csr_PMPCFG0 = 12'h3A0; // Physical memory protection configuration (MRW)
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RVCSRIndex csr_PMPCFG15 = 12'h3AF;
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RVCSRIndex csr_PMPADDR0 = 12'h3B0; // Physical memory protection address register (MRW)
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RVCSRIndex csr_PMPADDR63 = 12'h3EF;
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// Debug/Trace Registers
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RVCSRIndex csr_TSELECT = 12'h7A0; // Debug/Trace trigger register select (MRW)
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RVCSRIndex csr_TDATA1 = 12'h7A1; // First Debug/Trace trigger data register (MRW)
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RVCSRIndex csr_TDATA2 = 12'h7A2; // Second Debug/Trace trigger data register (MRW)
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RVCSRIndex csr_TDATA3 = 12'h7A3; // Third Debug/Trace trigger data register (MRW)
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RVCSRIndex csr_MCONTEXT = 12'h7A8; // Machine-mode context register (MRW)
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// Debug Mode Registers
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RVCSRIndex csr_DCSR = 12'h7B0; // Debug Control and Status
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RVCSRIndex csr_DPC = 12'h7B1; // Debug Program Counter
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RVCSRIndex csr_DSCRATCH0 = 12'h7B2; // Debug Scratch Register 0
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RVCSRIndex csr_DSCRATCH1 = 12'h7B3; // Debug Scratch Register 1
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// Machine Counters/Timers
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RVCSRIndex csr_MCYCLE = 12'hB00; // Cycle counter for RDCYCLE instruction (MRW)
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RVCSRIndex csr_MINSTRET = 12'hB02; // Machine instructions-retired counter (MRW)
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RVCSRIndex csr_MHPMCOUNTER3 = 12'hB03; // Machine performance-monitoring counter (MRW)
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RVCSRIndex csr_MHPMCOUNTER4 = 12'hB04; // Machine performance-monitoring counter (MRW)
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RVCSRIndex csr_MHPMCOUNTER5 = 12'hB05; // Machine performance-monitoring counter (MRW)
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RVCSRIndex csr_MHPMCOUNTER6 = 12'hB06; // Machine performance-monitoring counter (MRW)
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RVCSRIndex csr_MHPMCOUNTER7 = 12'hB07; // Machine performance-monitoring counter (MRW)
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RVCSRIndex csr_MHPMCOUNTER8 = 12'hB08; // Machine performance-monitoring counter (MRW)
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RVCSRIndex csr_MHPMCOUNTER9 = 12'hB09; // Machine performance-monitoring counter (MRW)
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`ifdef RV32
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RVCSRIndex csr_MCYCLEH = 12'hB80; // Upper 32 bits of mcycle, RV32I only (MRW)
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RVCSRIndex csr_MINSTRETH = 12'hB82; // Upper 32 bits of minstret, RV32I only (MRW)
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RVCSRIndex csr_MHPMCOUNTER3H = 12'hB83; // Machine performance-monitoring counter (upper 32 bits) (MRW)
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RVCSRIndex csr_MHPMCOUNTER4H = 12'hB84; // Machine performance-monitoring counter (upper 32 bits) (MRW)
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RVCSRIndex csr_MHPMCOUNTER5H = 12'hB85; // Machine performance-monitoring counter (upper 32 bits) (MRW)
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RVCSRIndex csr_MHPMCOUNTER6H = 12'hB86; // Machine performance-monitoring counter (upper 32 bits) (MRW)
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RVCSRIndex csr_MHPMCOUNTER7H = 12'hB87; // Machine performance-monitoring counter (upper 32 bits) (MRW)
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RVCSRIndex csr_MHPMCOUNTER8H = 12'hB88; // Machine performance-monitoring counter (upper 32 bits) (MRW)
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RVCSRIndex csr_MHPMCOUNTER9H = 12'hB89; // Machine performance-monitoring counter (upper 32 bits) (MRW)
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`endif
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RVCSRIndex csr_CYCLE = 12'hC00; // Read only mirror of MCYCLE
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// Machine Information Registers
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RVCSRIndex csr_MVENDORID = 12'hF11; // Vendor ID (MRO)
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RVCSRIndex csr_MARCHID = 12'hF12; // Architecture ID (MRO)
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RVCSRIndex csr_MIMPID = 12'hF13; // Implementation ID (MRO)
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RVCSRIndex csr_MHARTID = 12'hF14; // Hardware thread ID (MRO)
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RVCSRIndex csr_MCONFIGPTR = 12'hF15; // Pointer to configuration data structure (MRO)
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//
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// RVCSRIndexOffset
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//
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typedef Bit#(8) RVCSRIndexOffset;
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// Trap Setup
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RVCSRIndexOffset csr_STATUS = 8'h00; // Status
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RVCSRIndexOffset csr_EDELEG = 8'h02; // Exception Delegation
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RVCSRIndexOffset csr_IDELEG = 8'h03; // Interrupt Delegation
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RVCSRIndexOffset csr_IE = 8'h04; // Interrupt Enable
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RVCSRIndexOffset csr_TVEC = 8'h05; // Vector Table
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RVCSRIndexOffset csr_COUNTEREN = 8'h06; // Counter Enable
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// Trap Handling
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RVCSRIndexOffset csr_SCRATCH = 8'h40; // Scratch Register
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RVCSRIndexOffset csr_EPC = 8'h41; // Exception Program Counter
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RVCSRIndexOffset csr_CAUSE = 8'h42; // Exception/Interrupt Cause
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RVCSRIndexOffset csr_TVAL = 8'h43; // Bad address or instruction
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RVCSRIndexOffset csr_IP = 8'h44; // Interrupt Pending
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//
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// RVCSROperator(s)
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//
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typedef RVFunc3 RVCSROperator;
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RVCSROperator csr_UNSUPPORTED_000 = 3'b000;
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RVCSROperator csr_CSRRW = 3'b001;
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RVCSROperator csr_CSRRS = 3'b010;
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RVCSROperator csr_CSRRC = 3'b011;
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RVCSROperator csr_UNSUPPORTED_100 = 3'b100;
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RVCSROperator csr_CSRRWI = 3'b101;
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RVCSROperator csr_CSRRSI = 3'b110;
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RVCSROperator csr_CSRRCI = 3'b111;
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//
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// RVExceptionCause(s)
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//
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typedef Bit#(4) RVExceptionCause;
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RVExceptionCause exception_INSTRUCTION_ADDRESS_MISALIGNED = 0;
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RVExceptionCause exception_INSTRUCTION_ACCESS_FAULT = 1;
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RVExceptionCause exception_ILLEGAL_INSTRUCTION = 2;
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RVExceptionCause exception_BREAKPOINT = 3;
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RVExceptionCause exception_LOAD_ADDRESS_MISALIGNED = 4;
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RVExceptionCause exception_LOAD_ACCESS_FAULT = 5;
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RVExceptionCause exception_STORE_ADDRESS_MISALIGNED = 6;
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RVExceptionCause exception_STORE_ACCESS_FAULT = 7;
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RVExceptionCause exception_ENVIRONMENT_CALL_FROM_U_MODE = 8;
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RVExceptionCause exception_ENVIRONMENT_CALL_FROM_S_MODE = 9;
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RVExceptionCause exception_RESERVED_10 = 10;
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RVExceptionCause exception_ENVIRONMENT_CALL_FROM_M_MODE = 11;
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RVExceptionCause exception_INSTRUCTION_PAGE_FAULT = 12;
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RVExceptionCause exception_LOAD_PAGE_FAULT = 13;
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RVExceptionCause exception_RESERVED_14 = 14;
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RVExceptionCause exception_STORE_PAGE_FAULT = 15;
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//
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// RVGPRIndex
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//
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typedef Bit#(5) RVGPRIndex;
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//
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// RVISAExtension
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//
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typedef Bit#(26) RVISAExtension;
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RVISAExtension isaext_A = 26'h000001; // Atomic extension
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RVISAExtension isaext_B = 26'h000002; // Tentatively reserved for Bit-Manipulation extension
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RVISAExtension isaext_C = 26'h000004; // Compressed extension
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RVISAExtension isaext_D = 26'h000008; // Double-precision floating-point extension
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RVISAExtension isaext_E = 26'h000010; // RV32E base ISA
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RVISAExtension isaext_F = 26'h000020; // Single-precision floating-point extension
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RVISAExtension isaext_G = 26'h000040; // __ RESERVED __
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RVISAExtension isaext_H = 26'h000080; // Hypervisor extension
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RVISAExtension isaext_I = 26'h000100; // RV32I/64I/128I base ISA
|
||||
RVISAExtension isaext_J = 26'h000200; // Tentatively reserved for Dynamically Translated Languages extension
|
||||
RVISAExtension isaext_K = 26'h000400; // __ RESERVED __
|
||||
RVISAExtension isaext_L = 26'h000800; // __ RESERVED __
|
||||
RVISAExtension isaext_M = 26'h001000; // Integer Multiply/Divide extension
|
||||
RVISAExtension isaext_N = 26'h002000; // Tentatively reserved for User-Level Interrupts extension
|
||||
RVISAExtension isaext_O = 26'h004000; // __ RESERVED __
|
||||
RVISAExtension isaext_P = 26'h008000; // Tentatively reserved for Packed-SIMD extension
|
||||
RVISAExtension isaext_Q = 26'h010000; // Quad-precision floating-point extension
|
||||
RVISAExtension isaext_R = 26'h020000; // __ RESERVED __
|
||||
RVISAExtension isaext_S = 26'h040000; // Supervisor mode implemented
|
||||
RVISAExtension isaext_T = 26'h080000; // __ RESERVED __
|
||||
RVISAExtension isaext_U = 26'h100000; // User mode implemented
|
||||
RVISAExtension isaext_V = 26'h200000; // Tentatively reserved for Vector extension
|
||||
RVISAExtension isaext_W = 26'h400000; // __ RESERVED __
|
||||
RVISAExtension isaext_X = 26'h800000; // Non-standard extensions present
|
||||
|
||||
//
|
||||
// RVInterruptCause(s)
|
||||
//
|
||||
typedef Bit#(4) RVInterruptCause;
|
||||
RVInterruptCause interrupt_SUPERVISOR_SOFTWARE_INTERRUPT = 1;
|
||||
RVInterruptCause interrupt_MACHINE_SOFTWARE_INTERRUPT = 3;
|
||||
RVInterruptCause interrupt_SUPERVISOR_TIMER_INTERRUPT = 5;
|
||||
RVInterruptCause interrupt_MACHINE_TIMER_INTERRUPT = 7;
|
||||
RVInterruptCause interrupt_SUPERVISOR_EXTERNAL_INTERRUPT = 9;
|
||||
RVInterruptCause interrupt_MACHINE_EXTERNAL_INTERRUPT = 11;
|
||||
|
||||
//
|
||||
// RVLoadOperator(s)
|
||||
//
|
||||
typedef RVFunc3 RVLoadOperator;
|
||||
RVLoadOperator load_LB = 3'b000;
|
||||
RVLoadOperator load_LH = 3'b001;
|
||||
RVLoadOperator load_LW = 3'b010;
|
||||
`ifdef RV32
|
||||
RVLoadOperator load_UNSUPPORTED_011 = 3'b011;
|
||||
`elsif RV64
|
||||
RVLoadOperator load_LD = 3'b011;
|
||||
`endif
|
||||
RVLoadOperator load_LBU = 3'b100;
|
||||
RVLoadOperator load_LHU = 3'b101;
|
||||
`ifdef RV32
|
||||
RVLoadOperator load_UNSUPPORTED_110 = 3'b110;
|
||||
`elsif RV64
|
||||
RVLoadOperator load_LWU = 3'b110;
|
||||
`endif
|
||||
RVLoadOperator load_UNSUPPORTED_111 = 3'b111;
|
||||
|
||||
//
|
||||
// RVOpcode
|
||||
//
|
||||
typedef Bit#(7) RVOpcode;
|
||||
RVOpcode opcode_AUIPC = 7'b0010111;
|
||||
RVOpcode opcode_BRANCH = 7'b1100011;
|
||||
RVOpcode opcode_JAL = 7'b1101111;
|
||||
RVOpcode opcode_JALR = 7'b1100111;
|
||||
RVOpcode opcode_LOAD = 7'b0000011;
|
||||
RVOpcode opcode_LUI = 7'b0110111;
|
||||
RVOpcode opcode_MISC_MEM = 7'b0001111;
|
||||
RVOpcode opcode_OP = 7'b0110011;
|
||||
RVOpcode opcode_OP_IMM = 7'b0010011;
|
||||
RVOpcode opcode_STORE = 7'b0100011;
|
||||
RVOpcode opcode_SYSTEM = 7'b1110011;
|
||||
|
||||
//
|
||||
// RVPrivilegeLevel
|
||||
//
|
||||
typedef Bit#(2) RVPrivilegeLevel;
|
||||
RVPrivilegeLevel priv_USER = 2'b00;
|
||||
RVPrivilegeLevel priv_SUPERVISOR = 2'b01;
|
||||
RVPrivilegeLevel priv_HYPERVISOR = 2'b10;
|
||||
RVPrivilegeLevel priv_MACHINE = 2'b11;
|
||||
|
||||
//
|
||||
// RVStoreOoperator(s)
|
||||
//
|
||||
typedef RVFunc3 RVStoreOperator;
|
||||
RVStoreOperator store_SB = 3'b000;
|
||||
RVStoreOperator store_SH = 3'b001;
|
||||
RVStoreOperator store_SW = 3'b010;
|
||||
`ifdef RV32
|
||||
RVStoreOperator store_UNSUPPORTED_011 = 3'b011;
|
||||
`elsif RV64
|
||||
RVStoreOperator store_SD = 3'b011;
|
||||
`endif
|
||||
RVStoreOperator store_UNSUPPORTED_100 = 3'b100;
|
||||
RVStoreOperator store_UNSUPPORTED_101 = 3'b101;
|
||||
RVStoreOperator store_UNSUPPORTED_110 = 3'b110;
|
||||
RVStoreOperator store_UNSUPPORTED_111 = 3'b111;
|
||||
|
||||
//
|
||||
// RVSystemOperator(s)
|
||||
//
|
||||
typedef Bit#(3) RVSystemOperator;
|
||||
RVSystemOperator sys_ECALL = 3'b000;
|
||||
RVSystemOperator sys_EBREAK = 3'b001;
|
||||
RVSystemOperator sys_SRET = 3'b010;
|
||||
RVSystemOperator sys_MRET = 3'b011;
|
||||
RVSystemOperator sys_WFI = 3'b100;
|
||||
18
src/ESeries.bsv
Normal file
18
src/ESeries.bsv
Normal file
@ -0,0 +1,18 @@
|
||||
//!submodule Cpu
|
||||
import Soc::*;
|
||||
|
||||
//!topmodule mkE001
|
||||
module mkE001(SocIfc#(32));
|
||||
SocCfg#(32) cfg = SocCfg {
|
||||
cpu_cfg: CpuCfg {}
|
||||
};
|
||||
let soc <- mkSoc(cfg);
|
||||
endmodule
|
||||
|
||||
//!topmodule mkE003
|
||||
module mkE003(SocIfc#(64));
|
||||
SocCfg#(64) cfg = SocCfg{
|
||||
cpu_cfg: CpuCfg {}
|
||||
};
|
||||
let soc <- mkSoc(cfg);
|
||||
endmodule
|
||||
22
src/Soc.bsv
Normal file
22
src/Soc.bsv
Normal file
@ -0,0 +1,22 @@
|
||||
import Cpu::*;
|
||||
export CpuCfg(..), mkSoc, SocCfg(..), SocIfc(..);
|
||||
|
||||
//
|
||||
// SocConfig
|
||||
//
|
||||
typedef struct {
|
||||
CpuCfg#(xlen) cpu_cfg;
|
||||
} SocCfg#(numeric type xlen);
|
||||
|
||||
//
|
||||
// SocIfc
|
||||
//
|
||||
interface SocIfc#(numeric type xlen);
|
||||
endinterface
|
||||
|
||||
//
|
||||
// mkSoc()
|
||||
//
|
||||
module mkSoc#(SocCfg#(xlen) cfg)(SocIfc#(xlen));
|
||||
let cpu <- mkCpu(cfg.cpu_cfg);
|
||||
endmodule
|
||||
12
tests/E001_tb.bsv
Normal file
12
tests/E001_tb.bsv
Normal file
@ -0,0 +1,12 @@
|
||||
//!topmodule mkE001_tb
|
||||
import ESeries::*;
|
||||
|
||||
module mkE001_tb(Empty);
|
||||
let soc <- mkE001();
|
||||
|
||||
rule run_it;
|
||||
// Required for test to pass.
|
||||
$display(">>>PASS");
|
||||
$finish();
|
||||
endrule
|
||||
endmodule
|
||||
12
tests/E003_tb.bsv
Normal file
12
tests/E003_tb.bsv
Normal file
@ -0,0 +1,12 @@
|
||||
//!topmodule mkE003_tb
|
||||
import ESeries::*;
|
||||
|
||||
module mkE003_tb(Empty);
|
||||
let soc <- mkE003();
|
||||
|
||||
rule run_it;
|
||||
// Required for test to pass.
|
||||
$display(">>>PASS");
|
||||
$finish();
|
||||
endrule
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user