From 086a91ae5b44ab0e5667204735be535519c794a9 Mon Sep 17 00:00:00 2001 From: John Terrell Date: Sat, 22 Apr 2023 22:41:47 -0700 Subject: [PATCH] WIP --- src/Cpu/Alu.bsv | 55 ++++--------------------------- src/Cpu/Alu_tb.bsv | 44 +++++++++++++++++++++++++ src/Cpu/CSRs/CsrFile.bsv | 5 +-- src/Cpu/CSRs/CsrFile_tb.bsv | 23 +++++++++++++ src/Cpu/CSRs/MachineISA_tb.bsv | 1 - src/Cpu/CSRs/MachineStatus_tb.bsv | 23 +++++++++++++ src/ESeries.bsv | 2 +- 7 files changed, 98 insertions(+), 55 deletions(-) create mode 100644 src/Cpu/Alu_tb.bsv create mode 100644 src/Cpu/CSRs/CsrFile_tb.bsv create mode 100644 src/Cpu/CSRs/MachineStatus_tb.bsv diff --git a/src/Cpu/Alu.bsv b/src/Cpu/Alu.bsv index 3c7a636..0edb15d 100644 --- a/src/Cpu/Alu.bsv +++ b/src/Cpu/Alu.bsv @@ -5,7 +5,7 @@ // reponsible for mathematical operations inside the CPU. // import RV_ISA::*; -export RV_ISA::*, AluCfg, AluIfc(..), mkAlu; +export AluCfg, AluIfc(..), mkAlu, Execute(..); function Maybe#(Bit#(32)) execute32(RVALUOperator operator, Bit#(32) operand1, Bit#(32) operand2); let sum = operand1 + operand2; @@ -83,10 +83,6 @@ instance Execute#(64); function execute = execute64; endinstance -instance Execute#(n); - function execute = tagged Invalid; -endinstance - typedef struct { } AluCfg#(numeric type xlen); @@ -94,51 +90,12 @@ interface AluIfc#(numeric type xlen); method Maybe#(Bit#(xlen)) execute(RVALUOperator operator, Bit#(xlen) operand1, Bit#(xlen) operand2); endinterface -module mkAlu#(AluCfg#(xlen) cfg)(AluIfc#(xlen)); +module mkAlu#(AluCfg#(xlen) cfg)(AluIfc#(xlen)) + provisos( + Execute#(xlen) + ); + method Maybe#(Bit#(xlen)) execute(RVALUOperator operator, Bit#(xlen) operand1, Bit#(xlen) operand2); return execute(operator, operand1, operand2); - - // return case(operator) - // alu_ADD: tagged Valid (operand1 + operand2); - // alu_SUB: tagged Valid (operand1 - operand2); - // alu_AND: tagged Valid (operand1 & operand2); - // alu_OR: tagged Valid (operand1 | operand2); - // alu_XOR: tagged Valid (operand1 ^ operand2); - // alu_SLTU: tagged Valid setLessThanUnsigned(operand1, operand2); - // alu_SLT: tagged Valid setLessThan(operand1, operand2); - - // alu_SLL: (xlen == 32 ? tagged Valid (operand1 << operand2[4:0]) : tagged Invalid); - // alu_SRA: (xlen == 32 ? tagged Valid signedShiftRight(operand1, operand2[4:0]) : tagged Invalid); - // alu_SRL: (xlen == 32 ? tagged Valid (operand1 >> operand2[4:0]) : tagged Invalid); - - // end else if (xlen == 64) begin - // alu_SLL: tagged Valid (operand1 << operand2[5:0]); - // alu_SRA: tagged Valid signedShiftRight(operand1, operand2[5:0]); - // alu_SRL: tagged Valid (operand1 >> operand2[5:0]); - - // alu_ADD32: begin - // let result = operand1[31:0] + operand2[31:0]; - // return tagged Valid signExtend(result[31:0]); - // end - // alu_SUB32: begin - // let result = (operand1[31:0] - operand2[31:0]); - // return tagged Valid signExtend(result[31:0]); - // end - // alu_SLL32: begin - // let result = (operand1[31:0] << operand2[4:0]); - // return tagged Valid signExtend(result[31:0]); - // end - // alu_SRA32: begin - // let result = signedShiftRight(operand1[31:0], operand2[4:0]); - // return tagged Valid signExtend(result[31:0]); - // end - // alu_SRL32: begin - // let result = (operand1[31:0] >> operand2[4:0]); - // return tagged Valid signExtend(result[31:0]); - // end - // end - - // default: tagged Invalid; - // endcase; endmethod endmodule diff --git a/src/Cpu/Alu_tb.bsv b/src/Cpu/Alu_tb.bsv new file mode 100644 index 0000000..aa79f97 --- /dev/null +++ b/src/Cpu/Alu_tb.bsv @@ -0,0 +1,44 @@ +import Alu::*; +import IsaCfg::*; +import RV_ISA::*; + +import Assert::*; + +module mkTopModule(Empty); + Reg#(Bit#(20)) stepNumber <- mkReg(0); + + // 32 bit ALU + AluCfg#(32) alucfg32 = AluCfg { + }; + AluIfc#(32) alu32 <- mkAlu(alucfg32); + + // 64 bit ALU + AluCfg#(64) alucfg64 = AluCfg { + }; + AluIfc#(64) alu64 <- mkAlu(alucfg64); + + (* no_implicit_conditions *) + rule test; + case(stepNumber) + 0: begin + Maybe#(Bit#(32)) result32 = execute(alu_ADD, 3, 1); + dynamicAssert(isValid(result32), "ALU32 - add returned invalid"); + dynamicAssert(result32.Valid == 4, "ALU32 - add result incorrect"); + + Maybe#(Bit#(64)) result64 = execute(alu_ADD, 3, 1); + dynamicAssert(isValid(result64), "ALU64 - add incorrect"); + dynamicAssert(result32.Valid == 4, "ALU64 - add result incorrect"); + end + + default: begin + dynamicAssert(stepNumber == 1, "ALU - not all tests run"); + $display(">>>PASS"); + $finish(); + end + endcase + endrule + + rule increment_step_number; + stepNumber <= stepNumber + 1; + endrule +endmodule \ No newline at end of file diff --git a/src/Cpu/CSRs/CsrFile.bsv b/src/Cpu/CSRs/CsrFile.bsv index bfb3090..de64964 100644 --- a/src/Cpu/CSRs/CsrFile.bsv +++ b/src/Cpu/CSRs/CsrFile.bsv @@ -70,19 +70,16 @@ module mkCsrFile#(CsrFileCfg#(xlen) cfg)(CsrFile#(xlen)) MachineStatus_Ifc#(xlen) mstatus <- mkMachineStatus(cfg.isa_cfg); MachineISA_Ifc#(xlen) misa <- mkMachineISA(cfg.isa_cfg); -/* ReadOnly#(Bit#(xlen)) mcycle <- mkReadOnly(truncate(cycleCounter)); ReadOnly#(Bit#(xlen)) mtimer <- mkReadOnly(truncate(timeCounter)); ReadOnly#(Bit#(xlen)) minstret <- mkReadOnly(truncate(retiredCounter)); -*/ -/* if (valueof(xlen) == 32) begin ReadOnly#(Bit#(xlen)) mcycleh <- mkReadOnly(truncateLSB(cycleCounter)); ReadOnly#(Bit#(xlen)) mtimeh <- mkReadOnly(truncateLSB(timeCounter)); ReadOnly#(Bit#(xlen)) minstreth <- mkReadOnly(truncateLSB(retiredCounter)); end -*/ + Reg#(Bit#(xlen)) mcause <- mkReg(0); Reg#(Bit#(xlen)) mtvec <- mkReg('hC0DEC0DE); Reg#(Bit#(xlen)) mepc <- mkReg(0); diff --git a/src/Cpu/CSRs/CsrFile_tb.bsv b/src/Cpu/CSRs/CsrFile_tb.bsv new file mode 100644 index 0000000..6fcf759 --- /dev/null +++ b/src/Cpu/CSRs/CsrFile_tb.bsv @@ -0,0 +1,23 @@ +import CsrFile::*; +import IsaCfg::*; + +import Assert::*; + +module mkTopModule(Empty); + Reg#(Bit#(20)) stepNumber <- mkReg(0); + + (* no_implicit_conditions *) + rule test; + case(stepNumber) + default: begin + dynamicAssert(stepNumber == 0, "CsrFile - not all tests run"); + $display(">>>PASS"); + $finish(); + end + endcase + endrule + + rule increment_step_number; + stepNumber <= stepNumber + 1; + endrule +endmodule diff --git a/src/Cpu/CSRs/MachineISA_tb.bsv b/src/Cpu/CSRs/MachineISA_tb.bsv index c602a0d..470e5a6 100644 --- a/src/Cpu/CSRs/MachineISA_tb.bsv +++ b/src/Cpu/CSRs/MachineISA_tb.bsv @@ -43,7 +43,6 @@ module mkTopModule(Empty); endcase endrule - rule increment_step_number; stepNumber <= stepNumber + 1; endrule diff --git a/src/Cpu/CSRs/MachineStatus_tb.bsv b/src/Cpu/CSRs/MachineStatus_tb.bsv new file mode 100644 index 0000000..5469d3c --- /dev/null +++ b/src/Cpu/CSRs/MachineStatus_tb.bsv @@ -0,0 +1,23 @@ +import MachineStatus::*; +import IsaCfg::*; + +import Assert::*; + +module mkTopModule(Empty); + Reg#(Bit#(20)) stepNumber <- mkReg(0); + + (* no_implicit_conditions *) + rule test; + case(stepNumber) + default: begin + dynamicAssert(stepNumber == 0, "MachineStatus - not all tests run"); + $display(">>>PASS"); + $finish(); + end + endcase + endrule + + rule increment_step_number; + stepNumber <= stepNumber + 1; + endrule +endmodule diff --git a/src/ESeries.bsv b/src/ESeries.bsv index 1634b1e..4281553 100644 --- a/src/ESeries.bsv +++ b/src/ESeries.bsv @@ -21,4 +21,4 @@ module mkE003(SocIfc#(64, 32)); } }; let soc <- mkSoc(cfg); -endmodule \ No newline at end of file +endmodule